SH7059 Datasheet, PDF (493/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
16.3.3 SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock phase, clock polarity, and communication clock rate of synchronous serial
communication.
Bit:
7
6
5
4
MLS
CPOS
CPHS
—
Initial value:
0
0
0
0
R/W: R/W
R/W
R/W
R/W
3
2
1
0
—
CKS2
CKS1
CKS0
0
0
0
0
R/W
R/W
R/W
R/W
Bit Bit Name
7
MLS
6
CPOS
5
CPHS
4, 3 ⎯
2
CKS2
1
CKS1
0
CKS0
Initial Value R/W
0
R/W
0
R/W
0
R/W
All 0
⎯
0
R/W
0
R/W
0
R/W
Description
MSB First/LSB First
Selects the serial data is communication in MSB first or LSB first.
0: LSB first (Initial value)
1: MSB first
Clock Polarity Selection
Selects SSCK clock polarity.
0: High output in idle mode, and low output in active mode (Initial value)
1: Low output in idle mode, and high output in active mode
Clock Phase Selection
Selects SSCK clock phase.
0: Data changes at the first edge. (Initial value)
1: Data is latched at the first edge.
Reserved
These bits are always read as 0. The write value should always be 0.
Communication Clock Rate Selection
Select the communication clock rate (prescaler division rate) when an
internal clock is selected.
000: Reserved (Initial value)
001: Pφ/4
010: Pφ/8
011: Pφ/16
100: Pφ/32
101: Pφ/64
110: Pφ/128
111: Pφ/256
SSMR is initialized by a power-on reset, hardware standby mode and software standby mode. It is not initialized by a
manual reset.
Rev.3.00 Mar. 12, 2008 Page 403 of 948
REJ09B0177-0300