SH7059 Datasheet, PDF (213/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
9.3.3 CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the RD, WRH, or WRL signal assert period beyond the length of the
CSn signal assert period by setting the SW3–SW0 bits of BCR2. This allows for flexible interfaces with external circuitry.
The timing is shown in figure 9.6. T_h and T_f cycles are added respectively before and after the ordinary cycle. Only CSn is
asserted in these cycles; RD, WRH, and WRL signals are not. Further, data is extended up to the T_f cycle, which is
effective for gate arrays and the like, which have slower write operations.
T_h
CK
T₁
T₂
T_f
Address
Read
Data
Write
,
Data
Figure 9.6 CS Assert Period Extension Function
9.4 Waits between Access Cycles
When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next
access. If there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle.
To enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the
same CS space by negating the CSn signal once.
9.4.1 Prevention of Data Bus Conflicts
For the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted
so that the number of idle cycles specified by the IW31 to IW00 bits of BCR2 occur. When idle cycles already exist
between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are
inserted.
Figure 9.7 shows an example of idles between cycles. In this example, one idle between CSn space cycles has been
specified, so when a CSm space write immediately follows a CSn space read cycle, one idle cycle is inserted.
Rev.3.00 Mar. 12, 2008 Page 123 of 948
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