SH7059 Datasheet, PDF (433/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
13. Watchdog Timer (WDT)
WOVF
13.4 Usage Notes
Figure 13.7 Timing of Setting WOVF
13.4.1 TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority
and the timer counter is not incremented (figure 13.8).
TCNT write cycle
T1
T2
T3
CK
Address
Internal
write signal
TCNT
input clock
TCNT address
TCNT
N
M
Counter write data
Figure 13.8 Contention between TCNT Write and Increment
13.4.2 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while the WDT is running, the
count may not increment correctly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the
values of bits CKS2 to CKS0.
13.4.3 Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between
interval timer mode and watchdog timer mode.
Rev.3.00 Mar. 12, 2008 Page 343 of 948
REJ09B0177-0300