SH7059 Datasheet, PDF (231/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits
DMAC Transfer DMAC Transfer
RS4 RS3 RS2 RS1 RS0 Request Source Request Signal
Transfer
Source
Transfer
Destination
Bus Mode
0
0
0
0
1
SCI0 transmit block TXI0 (SCI0 transmit- Don't care* TDR0
data-empty transfer
request)
Cycle-steal
1
0
SCI0 receive block RXI0 (SCI0 receive-data- RDR0
full transfer request)
Don't care*
Cycle-steal
1
SCI1 transmit block TXI1 (SCI1 transmit- Don't care* TDR1
data-empty transfer
request)
Cycle-steal
1
0
0
SCI1 receive block RXI1 (SCI1 receive-data- RDR1
full transfer request)
Don't care*
Cycle-steal
1
SCI2 transmit block TXI2 (SCI2 transmit- Don't care* TDR2
data-empty transfer
request)
Cycle-steal
1
0
SCI2 receive block RXI2 (SCI2 receive-data- RDR2
full transfer request)
Don't care*
Cycle-steal
1
SCI3 transmit block TXI3 (SCI3 transmit- Don't care* TDR3
data-empty transfer
request)
Cycle-steal
1
0
0
0
SCI3 receive block RXI3 (SCI3 receive-data- RDR3
full transfer request)
Don't care*
Cycle-steal
1
SCI4 transmit block TXI4 (SCI4 transmit- Don't care* TDR4
data-empty transfer
request)
Cycle-steal
1
0
SCI4 receive block RXI4 (SCI4 receive-data- RDR4
full transfer request)
Don't care*
Cycle-steal
1
A/D0
ADI0 (A/D0
ADDR0–
conversion end interrupt) ADDR11
Don't care*
Burst/cycle-
steal
1
0
0
A/D1
ADI1 (A/D1
ADDR12–
conversion end interrupt) ADDR23
Don't care*
Burst/cycle-
steal
1
A/D2
ADI2 (A/D2
ADDR24–
conversion end interrupt) ADDR31
Don't care*
Burst/cycle-
steal
1
0
SSU0 transmit block SSTSI0 (transmit-
Don't care* SSTDR0_0 to Cycle-steal
data-empty or
SSTDR3_0
transmit-end transfer
request of SSU0)
1
HCAN0
RM0 (HCAN0
receive interrupt)
MB0–MB31 Don't care*
Burst/cycle-
steal
1
0
0
0
0
SSU0 receive block SSRXI0 (receive-data- SSRDR0_0 to Don't care*
Cycle-steal
full transfer request of SSRDR3_0
SSU0)
1
ATU-II
ICI0A (ICR0A input
capture generation)
Don't care* Don't care*
Burst/cycle-
steal
1
0
ATU-II
ICI0B (ICR0B input
capture generation)
Don't care* Don't care*
Burst/cycle-
steal
1
ATU-II
ICI0C (ICR0C input
capture generation)
Don't care* Don't care*
Burst/cycle-
steal
1
0
0
ATU-II
ICI0D (ICR0D input
capture generation)
Don't care* Don't care*
Burst/cycle-
steal
1
ATU-II
CMI6A (CYLR6A
compare-match
generation)
Don't care* Don't care*
Burst/cycle-
steal
Rev.3.00 Mar. 12, 2008 Page 141 of 948
REJ09B0177-0300