SH7059 Datasheet, PDF (660/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Advanced User Debugger (AUD)
21.4.3 Operation
Operation starts in RAM monitor mode when AUDMD is driven high after AUDRST has been asserted, then AUDRST is
negated*.
Figure 21.5 shows an example of a read operation, and figure 21.6 an example of a write operation.
When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address, or data (writing only) is
input in the format shown in figure 21.2, execution of read/write access to the specified address is started. During internal
execution, the AUD returns Not Ready (0000). When execution is completed, the Ready flag (0001) is returned (figures
21.5 and 21.6). Table 21.2 shows the Ready flag format.
In a read, data of the specified size is output when AUDSYNC is negated following detection of this flag (figure 21.7).
If a command other than the above is input in DIR, the AUD treats this as a command error, disables processing, and sets
bit 1 in the Ready flag to 1. If a read/write operation initiated by the command specified in DIR causes a bus error, the
AUD disables processing and sets bit 2 in the Ready flag to 1 (figure 21.7).
Table 21.2 Ready Flag Format
Bit 3
Fixed at 0
Bit 2
0: Normal status
1: Bus error
Bit 1
0: Normal status
1: Bus error
Bit 0
0: Not ready
1: Ready
Bus error conditions are shown below.
1. Word access to address 4n+1 or 4n+3
2. Longword access to address 4n+1, 4n+2, or 4n+3
3. Longword access to on-chip I/O 8-bit space
4. Access to external space in single-chip mode
AUDCK
AUDATAn
AUDCK
AUDATAn
0000 1000 A3–A0
DIR
Input
Input/output switchover
A31–A28
0000
Not ready
0001
Ready
0001 0001 D3–D0 D7–D4
Ready Ready
Output
Figure 21.5 Example of Read Operation (Byte Read)*
0000 1110 A3–A0
DIR
Input/output switchover
A31–A28 D3–D0
D31–D28
0000
Not ready
Input
0001
Ready
Output
0001 0001
Ready Ready
Figure 21.6 Example of Write Operation (Longword Write)*
Rev.3.00 Mar. 12, 2008 Page 570 of 948
REJ09B0177-0300