SH7059 Datasheet, PDF (180/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
• Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine
the NMI pin level. This bit cannot be modified.
Bit 15: NMIL
0
1
Description
NMI input level is low
NMI input level is high
• Bits 14 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—NMI Edge Select (NMIE)
Bit 8: NMIE
0
1
Description
Interrupt request is detected on falling edge of NMI input (Initial value)
Interrupt request is detected on rising edge of NMI input
• Bits 7 to 0—IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): These bits set the IRQ0–IRQ7 interrupt request detection
mode.
Bits 7-0: IRQ0S–IRQ7S
0
1
Description
Interrupt request is detected on low level of IRQ input (Initial value)
Interrupt request is detected on falling edge of IRQ input
7.3.3 IRQ Status Register (ISR)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
IRQ0F
0
R/W
6
IRQ1F
0
R/W
5
IRQ2F
0
R/W
4
IRQ3F
0
R/W
3
IRQ4F
0
R/W
2
IRQ5F
0
R/W
1
IRQ6F
0
R/W
0
IRQ7F
0
R/W
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0–IRQ7. When
IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing 0 to IRQnF after reading
IRQnF = 1.
A reset, hardware standby mode, and software standby mode initialize ISR.
• Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Rev.3.00 Mar. 12, 2008 Page 90 of 948
REJ09B0177-0300