SH7059 Datasheet, PDF (535/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Examples:
1. To have a bit rate of 1 Mbps with a Pφ (peripheral clock) frequency of fclk = 20 MHz, it is possible to set: BRP[7:0] =
1, TSEG1[3:0] = 5, and TSEG2[2:0] = 2. Then BCR1 should be written to H'5200 and BCR0 to H'0001.
2. To have a bit rate of 500 kbps with a Pφ (peripheral clock) frequency of fclk = 16 MHz, it is possible to set: BPR[7:0]
= 1, TSEG1[3:0] = 9, TSEG2[2:0] = 4. Then BCR1 should be written to H'9400 and BCR0 to H'0001.
17.4.5 Interrupt Register_n (IRR_n) (n = 0, 1)
The interrupt register (IRR) is a 16-bit readable/writable register that contains status flags for the various interrupt sources.
• IRR
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRR IRR IRR IRR IRR IRR IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0
15 14 13 12 11 10
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R/W: R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R R R/W
Bit
Bit Name Initial Value R/W Description
15
IRR15
0
R/W Timer Compare Match Interrupt Flag 1
Indicates that a compare-match condition occurred to the timer compare
match register 1 (TCMR1). When the value set in TCMR1 matches the timer
value (TCMR1 = TCNTR), this bit is set. This bit is not set if the TCMR1
value is H'0000.
0: Timer compare match has not occurred to TCMR1
Clearing condition: Writing 1
1: Timer compare match has occurred to TCMR1
Setting condition: TCMR1 matches the timer value (TCMR1 = TCNTR) if
TMR1 = 0 or matches Cycle_Count + TCNTR[15:4] if TMR1 = 1
14
IRR14
0
R/W Timer Compare Match Interrupt Flag 0
Indicates that a compare-match condition occurred to the timer compare
match register 0 (TCMR0). When the value set in TCMR0 matches the timer
value (TCMR0 = TCNTR), this bit is set. This bit is not set if the TCMR0
value is H'0000.
0: Timer compare match has not occurred to the TCMR0
Clearing condition: Writing 1
1: Timer compare match has occurred to the TCMR0
Setting condition: TCMR0 matches the timer value (TCMR0 = TCNTR)
13
IRR13
0
R/W Timer Overrun Interrupt Flag
Indicates that the timer has overrun and is reset to the LOSR (local offset
register) value. This bit is set even when TCMR0 is enabled to clear/set the
timer value and its value is set to H'FFFF.
0: Timer has not overrun
Clearing condition: Writing 1
1: Timer has overrun
Setting condition: When the timer (TCNTR) changes from H'FFFF to
H'0000
Rev.3.00 Mar. 12, 2008 Page 445 of 948
REJ09B0177-0300