SH7059 Datasheet, PDF (631/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20.3 Register Descriptions
20. High-performance User Debug Interface (H-UDI)
20.3.1 Instruction Register (SDIR)
Bit: 15
14
13
12
11
10
9
8
TS3 TS2 TS1 TS0
—
—
—
—
Initial value: 1
1
1
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. H-UDI instructions can be transferred
to SDIR by serial input from TDI. SDIR can be initialized by the TRST signal or in software standby mode, but is not
initialized by a reset.
SDIR defines four valid bits for instruction. If an instruction exceeding four bits is input, the last four bits of the serial data
will be stored in SDIR.
Operation is not guaranteed if a reserved instruction is set in this register.
Bits 15 to 12—Test Set Bits (TS3–TS0): Table 20.4 shows the instruction configuration.
Table 20.4 Instruction Configuration
Bit 15:
TS3
0
Bit 14:
TS2
0
Bit 13:
TS1
0
1
1
0
1
1
0
0
1
1
0
1
Bit 12:
TS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
EXTEST mode
Reserved
CLAMP mode
HIGHZ mode
SAMPLE/PRELOAD mode
Reserved
Reserved
Reserved
Reserved
Reserved
H-UDI interrupt
Reserved
Reserved
Reserved
IDCODE mode
(Initial value)
BYPASS mode
Bits 11 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev.3.00 Mar. 12, 2008 Page 541 of 948
REJ09B0177-0300