SH7059 Datasheet, PDF (191/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. User Break Controller (UBC)
8.2.3 User Break Bus Cycle Register (UBBR)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
CP1
CP0
ID1
ID0
RW1
RW0
SZ1
SZ0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from among the following four
break conditions:
1. CPU cycle/DMA cycle
2. Instruction fetch/data access
3. Read/write
4. Operand size (byte, word, longword)
UBBR is initialized to H'0000 by a power on reset, in module standby mode, and in software standby mode.
• Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
• Bits 7 and 6—CPU Cycle/DMA Cycle Select (CP1, CP0): These bits designate break conditions for CPU cycles or
DMA cycles.
Bit 7: CP1
0
1
Bit 6: CP0
0
1
0
1
Description
No user break interrupt occurs
Break on CPU cycles
Break on DMA cycles
Break on both CPU and DMA cycles
(Initial value)
• Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to break on instruction fetch
and/or data access cycles.
Bit 5: ID1
0
1
Bit 4: ID0
0
1
0
1
Description
No user break interrupt occurs
Break on instruction fetch cycles
Break on data access cycles
Break on both instruction fetch and data access cycles
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 101 of 948
REJ09B0177-0300