SH7059 Datasheet, PDF (188/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. User Break Controller (UBC)
8.1.2 Block Diagram
Figure 8.1 shows a block diagram of the UBC.
Module bus
Bus
interface
UBCR
UBBR
UBAMRH UBARH
UBAMRL UBARL
Break condition
comparator
User break
interrupt
generating
circuit
Trigger output
generating
circuit
Interrupt request
Interrupt controller
UBCTRG pin output
Legend:
UBARH, UBARL: User break address registers H, L
UBAMRH, UBAMRL: User break address mask registers H, L
UBBR:
User break bus cycle register
UBCR:
User break control register
Figure 8.1 User Break Controller Block Diagram
8.1.3 Register Configuration
The UBC has the six registers shown in table 8.1. Break conditions are established using these registers.
Table 8.1 Register Configuration
Name
Abbr.
R/W
Initial Value Address*
Access Size
User break address register H
UBARH
R/W
H'0000
H'FFFFEC00
8, 16, 32
User break address register L
UBARL
R/W
H'0000
H'FFFFEC02
8, 16, 32
User break address mask register H
UBAMRH
R/W
H'0000
H'FFFFEC04
8, 16, 32
User break address mask register L
UBAMRL
R/W
H'0000
H'FFFFEC06
8, 16, 32
User break bus cycle register
UBBR
R/W
H'0000
H'FFFFEC08
8, 16, 32
User break control register
UBCR
R/W
H'0000
H'FFFFEC0A
8, 16, 32
Note: * In register access, four cycles are required for byte access and word access, and eight cycles for longword
access.
Rev.3.00 Mar. 12, 2008 Page 98 of 948
REJ09B0177-0300