SH7059 Datasheet, PDF (248/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
⎯ Channel 9 compare-match signal can be captured as trigger (channel 3 only)
⎯ Compare-match interrupts/capture interrupts can be generated
• Channels 6 and 7 have four 16-bit duty registers, four cycle registers, and four buffer registers, allowing the following
operations:
⎯ Any cycle and duty from 0 to 100% can be set
⎯ Duty buffer register value transferred to duty register every cycle
⎯ Interrupts can be generated every cycle
⎯ Complementary PWM output can be set (channel 6 only)
• Channel 8 has sixteen 16-bit down-counters for one-shot pulse output, allowing the following operations:
⎯ One-shot pulse generation by down-counter
⎯ Down-counter can be rewritten during count
⎯ Interrupt can be generated at end of down-count
⎯ Offset one-shot pulse function available
⎯ Can be linked to channel 1 and 2 output compare functions
⎯ Reload function can be set to eight 16-bit down-counters (DCNT8I to DCNT8P)
• Channel 9 has six event counters and six general registers, allowing the following operations:
⎯ Event counters can be cleared by compare-match
⎯ Rising-edge, falling-edge, or both-edge detection available for external input
⎯ Compare-match signal can be input to channel 3
• Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit free-running counter,
output compare/input capture register, reload register, 8-bit event counter, and output compare register, and 16-bit
reload counter, allowing the following operations:
⎯ Capture on external input pin edge input
⎯ Reload count possible with 1/32, 1/64, 1/128, or 1/256 times the captured value
⎯ Internal clock generated by reload counter underflow can be used as 16-bit free-running counter input
⎯ Channel 1 and 2 free-running counter clearing capability
• Channel 11 has one 16-bit free-running counter and two 16-bit general registers, allowing the following operations:
⎯ Two general registers can be used for input capture/output compare
⎯ Waveform output at compare-match: Selection of 0, 1, or toggle output
⎯ Input capture function: Selection of rising edge, falling edge, or both edge detection
⎯ Compare-match signal can be output to APC by using a general register as an output compare register
• High-speed access to internal 16-bit bus
⎯ High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and capture registers
• 75 interrupt sources
⎯ Four input capture interrupt requests, one overflow interrupt request, and one interval interrupt request for channel
0
⎯ Sixteen dual input capture/compare-match interrupt requests and two counter overflow interrupt requests for
channels 1 and 2
⎯ Twelve dual input capture/compare-match interrupt requests and three overflow interrupt requests for channels 3 to
5
⎯ Eight compare-match interrupts for channels 6 and 7
⎯ Sixteen one-shot end interrupt requests for channel 8
⎯ Six compare-match interrupts for channel 9
⎯ Two compare-match interrupts and one dual-function input capture/compare-match interrupt for channel 10
⎯ Two dual input capture/compare-match interrupt requests and one overflow interrupt request for channel 11
Rev.3.00 Mar. 12, 2008 Page 158 of 948
REJ09B0177-0300