SH7059 Datasheet, PDF (687/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Pin Function Controller (PFC)
The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in
port F. Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ/SCS1 to PF0/A16. PFIOR is enabled when port F pins
function as general input/output pins (PF15 to PF0), and disabled otherwise.
When port F pins function as PF15 to PF0, a pin becomes an output when the corresponding bit in PFIOR is set to 1, and
an input when the bit is cleared to 0.
PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in
software standby mode. It is not initialized in sleep mode. It is not initialized by a WDT power-on reset.
22.3.13 Port F Control Registers H and L (PFCRH, PFCRL)
Port F control registers H and L (PFCRH, PFCRL) are 16-bit readable/writable registers that select the functions of the 16
multiplex pins in port F and the function of the CK pin. PFCRH selects the functions of the pins for the upper 8 bits of port
F, and PFCRL selects the functions of the pins for the lower 8 bits.
PFCRH and PFCRL are initialized to H'0015 and H'5000, respectively, by a power-on reset (excluding a WDT power-on
reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode.
Port F Control Register H (PFCRH)
Bit: 15
14
13
12
11
10
9
8
CKHIZ PF15MD PF15MD PF14MD PF14MD PF13MD — PF12MD
0
1
0
1
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W
R
R/W
Bit: 7
6
5
4
3
2
1
0
— PF11MD — PF10MD — PF9MD — PF8MD
Initial value: 0
0
0
1
0
1
0
1
R/W: R
R/W
R
R/W
R
R/W
R
R/W
• Bit 15—CKHIZ Bit: Selects the function of pin CK.
Bit: CKHIZ
0
1
Description
CK pin output
CK pin Hi-Z
(Initial value)
• Bits 14 and 13—PF15 Mode Bit 0, 1 (PF15MD0, PF15MD1): Selects the function of pin PF15/BREQ/SCS1.
Bit 14: PF15MD0
0
1
Bit 13: PF15MD1
0
1
0
1
Expanded Mode
General input/output (PF15)
(Initial value)
Reserved (Do not set)
Bus request input (BREQ)
Reserved (Do not set)
Description
Single-Chip Mode
General input/output (PF15)
(Initial value)
Chip select input/output (SCS1)
General input/output (PF15)
Rev.3.00 Mar. 12, 2008 Page 597 of 948
REJ09B0177-0300