SH7059 Datasheet, PDF (14/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
7.5 Interrupt Response Time
Table 7.5 Interrupt Response Time (Multiplication Ratio of
8)
122
Number of States
Item
Peripheral
Module NMI
IRQ
Synchronizing input signal 0 or 6
(synchronized with peripheral [0 or 3]
clock Pφ) with internal clock
and DMAC activation
judgment
1 to 4
[1 or 2]
6 to 9
[3 to 5]
Notes
For the number of states
required for each interrupt,
see the note (*) below.
The values enclosed in [ ]
are values for when the
multiplication ratio is 4.
7.5 Interrupt Response Time
Table 7.5 Interrupt Response Time
Table amended
Number of States
Item
Peripheral Module NMI
IRQ
Synchronizing input signal
(synchronized with
peripheral clock P ) with
internal clock and DMAC
activation judgment
0 or 6
1 to 4
6 to 9
Notes
For the number of states
required for each interrupt,
see the note below.
8.2.1 User Break Address Register (UBAR)
128
UBARH and UBARL are initialized to H'0000 by a power-on
reset and in module standby mode. They are not initialized
in software standby mode.
8.2.1 User Break Address Register (UBAR)
Description amended
UBARH and UBARL are initialized to H'0000 by a power-on
reset, in module standby mode, and in software standby
mode.
8.2.2 User Break Address Mask Register (UBAMR)
129
UBAMRH and UBAMRL are initialized to H'0000 by a
power-on reset and in module standby mode. They are not
initialized in software standby mode.
8.2.2 User Break Address Mask Register (UBAMR)
Description amended
UBAMRH and UBAMRL are initialized to H'0000 by a
power-on reset, in module standby mode, and in software
standby mode.
8.2.3 User Break Bus Cycle Register (UBBR)
130
UBBR is initialized to H'0000 by a power on reset and in
module standby mode. It is not initialized in software
standby mode.
8.2.3 User Break Bus Cycle Register (UBBR)
Description amended
UBBR is initialized to H'0000 by a power on reset, in
module standby mode, and in software standby mode.
8.2.4 User Break Control Register (UBCR)
132
8.2.4 User Break Control Register (UBCR)
Description amended
UBCR is initialized to H'0000 by a power-on reset and in
module standby mode. It is not initialized in software
standby mode.
UBCR is initialized to H'0000 by a power-on reset, in
module standby mode, and in software standby mode.
Bits 2 and 1—Clock Select 1 and 0 (CKS1, CKS0)
Bits 2 and 1—Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the
UBCTRG signal output in the event of a condition match.
Bit 2: CKS1
0
Bit 1: CKS0
0
Description
When the internal clock is four times an input clock, UBCTRG
pulse width is φ/2
When the internal clock is eight times an input clock, UBCTRG
pulse width is φ/4
(Initial value)
Notes: φ: Internal clock
See section 8.5.7, Internal Clock (φ) Multiplication Ratio
and UBCTRG Pulse Width.
8.5.7 Internal Clock (φ) Multiplication Ratio and UBCTRG
Pulse Width
140
9.1.2 Block Diagram
Figure 9.1 BSC Block Diagram
142
Bits 2 and 1—Clock Select 1 and 0 (CKS1, CKS0)
Bit 2: CKS1
0
Bit 1: CKS0
0
Description
UBCTRG pulse width is φ/4
(Initial value)
Notes: φ: Internal clock
8.5.7 Internal Clock (φ) Multiplication Ratio and UBCTRG
Pulse Width
Deleted
9.1.2 Block Diagram
Figure 9.1 BSC Block Diagram
Bus arbitration control unit added
BREQ
BACK
Bus
arbitration
control unit
Rev.3.00 Mar. 12, 2008 Page xiv of xc
REJ09B0177-0300