SH7059 Datasheet, PDF (204/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
Table 9.5 Number of Access Cycles for Peripheral Module Registers
Module Name
Bus Width
ROM
8
UBC, WDT, BSC, DMAC, INTC
16
SCI
8
ATU, APC, CMT, PORT, HUDI, CPG, and power- 16
down state
AD, MTAD
8
SSU*
16
HCAN
16
Note: * SSU: Synchronous Serial Communication Unit
Number of Access Cycles
Byte: 4
Byte and word: 4, longword: 8
Byte: 8 to 11, word: 16 to 19
Byte and word: 8 to 11, longword: 16 to 19
Byte: 12 to 15, word: 24 to 27
Byte and word: 12 to 15, longword: 24 to 27
Byte and word: 12 to 15 + wait
9.2 Description of Registers
9.2.1 Bus Control Register 1 (BCR1)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
A3SZ
A2SZ
A1SZ
A0SZ
Initial value:
0
0
0
0
1
1
1
1
R/W:
R
R
R
R
R/W
R/W
R/W
R/W
BCR1 is a 16-bit readable/writable register that specifies the bus size of the CS spaces.
Write bits 15–0 of BCR1 during the initialization stage after a power-on reset, and do not change the values thereafter. In
on-chip ROM enabled mode, do not access any of the CS spaces until after completion of register initialization. In on-chip
ROM disabled mode, do not access any CS space other than CS0 until after completion of register initialization.
BCR1 is initialized to H'000F by a power-on reset, in hardware standby mode, and in software standby mode. It is not
initialized by a manual reset.
• Bits 15–4—Reserved: The write value should always be 0. Operation cannot be guaranteed if 1 is written to these bits.
• Bit 3—CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size. A 0 setting specifies byte (8-bit) size,
and a 1 setting specifies word (16-bit) size.
Bit 3: A3SZ
0
1
Description
Byte (8-bit) size
Word (16-bit) size
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 114 of 948
REJ09B0177-0300