SH7059 Datasheet, PDF (53/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
23.4.4 RAM Emulation Register (RAMER)
Table 23.7 Overlapping of RAM Area and User MAT Area
862, 863
… RAMER is initialized to H'0000 at a power-on reset or in
hardware standby mode and is not initialized in software
standby mode.
SH7058S/SH7059
25.4.4 RAM Emulation Register (RAMER)
Table 25.7 Overlapping of RAM Area and User MAT Area
Bit table amended
… RAMER is initialized to H'0000 at a power-on reset or in
hardware standby mode, or in software standby mode.
Bit :
7
Initial value : 0
R/W :
R
Bit :
7
2
1
0
RAM2 RAM1 RAM0 _{Initial value : 0}
0
0
0
R/W :
R
R/W
R/W
R/W
2
1
0
RAM0
0
0
0
R
R
R/W
23.5.1 Boot Mode
864
…After the SCI bit rate is automatically adjusted, the
communication with the host is executed by means of the
control command method.
(1) SCI Interface Setting by Host
Table 23.8 System Clock Frequency that Can
Automatically Adjust Bit Rate of This LSI
865
Host Bit Rate
9,600 bps
19,200 bps
System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate
20 to 40 MHz (input frequency of 5 to 10 MHz)
20 to 40 MHz (input frequency of 5 to 10 MHz)
Table replaced
25.5.1 Boot Mode
Description added
…After the SCI bit rate is automatically adjusted, the
communication with the host is executed by means of the
control command method. The RAM areas used by boot
mode are 3 Kbytes starting at address H'FFFE8000, 4
Kbytes starting at address H'FFFFB000, and 128 bytes
from H'FFFFBF80 to H'FFFFBFFF, which are used as the
stack.
(1) SCI Interface Setting by Host
Table 25.8 System Clock Frequency that Can
Automatically Adjust Bit Rate of This LSI
Table amended
Host Bit Rate
9,600 bps
19,200 bps
System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate
40 to 80 MHz (input frequency of 5 to 10 MHz)
40 to 80 MHz (input frequency of 5 to 10 MHz)
23.5.2 User Program Mode
(1) On-Chip RAM Address Map when
Programming/Erasing is Executed
Figure 23.10 RAM Map after Download
869
Area to be downloaded (Size: 2 kbytes)
25.5.2 User Program Mode
(1) On-Chip RAM Address Map when
Programming/Erasing is Executed
Figure 25.10 RAM Map after Download
Figure amended
Area to be downloaded (Size: 3 kbytes)
Address
RAMTOP (H'FFFF0000)
FTDAR setting+2048
(2.3) VBR is cleared to 0 and 1 is written to the SCO bit of
FCCS, and then download is executed.
871
… Four NOP instructions are executed immediately after
the instructions that set the SCO bit to 1.
Address
RAMTOP (H'FFFE8000)
FTDAR setting+3072
(2.3) VBR is cleared to 0 and 1 is written to the SCO bit of
FCCS, and then download is executed.
Description amended
… Eight NOP instructions are executed immediately after
the instructions that set the SCO bit to 1.
Rev.3.00 Mar. 12, 2008 Page liii of xc
REJ09B0177-0300