SH7059 Datasheet, PDF (438/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Compare Match Timer (CMT)
• Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock input to CMCNT from among the four
internal clocks obtained by dividing the peripheral clock (Pφ). When the STR bit of CMSTR is set to 1, CMCNT
begins incrementing with the clock selected by CKS1 and CKS0.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
Pφ/8
Pφ/32
Pφ/128
Pφ/512
(Initial value)
14.2.3 Compare Match Timer Counter (CMCNT)
The compare match timer counter (CMCNT) is a 16-bit register used as an up-counter for generating interrupt requests.
When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR bit of CMSTR is set
to 1, CMCNT begins incrementing with that clock. When the CMCNT value matches that of the compare match timer
constant register (CMCOR), CMCNT is cleared to H'0000 and the CMF flag of CMCSR is set to 1. If the CMIE bit of
CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested.
CMCNT is initialized to H'0000 by a power-on reset and in the standby modes. It is not initialized by a manual reset.
Bit:
15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14.2.4 Compare Match Timer Constant Register (CMCOR)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for compare match with
CMCNT.
CMCOR is initialized to H'FFFF by a power-on reset and in the standby modes. It is not initialized by a manual reset.
Bit:
15
14
13
12
11
10
9
8
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev.3.00 Mar. 12, 2008 Page 348 of 948
REJ09B0177-0300