SH7059 Datasheet, PDF (796/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
• Operating frequency error
The operating frequency is calculated from the received value of the input frequency and the multiplication or
division ratio. The input frequency is input to the LSI and the LSI is actually operated at the operating
frequency. The expression is given below.
Operating frequency = Input frequency*Multiplication ratio, or
Operating frequency = Input frequency/Division ratio
The calculated operating frequency should be checked to ensure that it is within the range of minimum to
maximum frequencies which are available with the clock modes of the specified device. When it is out of this
range, an operating frequency error is generated.
• Bit rate
From peripheral operating clock (φ) and bit rate (B), the clock select (CKS) value (n) in the serial mode register
(SMR) and the bit rate register (BRR) value (N) are obtained. The error between n and N that is calculated by
the method below is checked to ensure that it is less than 4%. When it is 4% or more, a bit-rate selection error
is generated.
Error (%) = {[
φ × 10⁶
] –1} × 100
(N+1) × B × 64 × 2^(2n-1)
When the new bit rate is selectable, the new bit rate will be set in the register after sending ACK in response.
The host will send ACK with the new bit rate for confirmation and the boot program will response with that
rate.
Confirmation H'06
⎯ Confirmation: H'06 (one byte): Confirmation of a new bit rate
Response H'06
⎯ Response: H'06 (one byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 24.29.
Host
Waiting for one-bit period
at the specified bit rate
Setting a new bit rate
H'06 (ACK)
Boot program
Setting a new bit rate
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
Setting a new bit rate
Figure 24.29 New Bit-Rate Selection Sequence
Transition to Programming/Erasing State: To enter the programming/erasing state, the boot program will transfer the
erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be
returned and a transition is made to the programming/erasing state.
The host should select the device code, clock mode, and new bit rate with device selection, clock-mode selection, and new
bit-rate selection commands, and then send the command for the transition to programming/erasing state. This procedure
should be carried out before transferring the programming selection command or program data.
Command H'40
⎯ Command: H'40 (one byte): Transition to programming/erasing state
Rev.3.00 Mar. 12, 2008 Page 706 of 948
REJ09B0177-0300