SH7059 Datasheet, PDF (379/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
When the ITVA bit for the desired timing is set, the A/D converter is activated when the corresponding bit of TCNT0
changes to 1.
When the ITVE bit for the desired timing is set, an interrupt can be requested when the corresponding bit of TCNT0
changes to 1. At this time, the corresponding bit of the timer status register (TSR0) is set. There are four interrupt sources
for the respective ITVRR registers, but there is only one interrupt vector.
To suppress interrupts and A/D converter activation, ITVRR bits should be cleared to 0.
An example of interval timer function operation is shown in figure 11.19.
In the example in figure 11.19, TCNT0 is started by setting ITVE to 1 in ITVRR1.
Pφ
TCNT0
Clock
TCNT0 0000003C 0000003D 0000003E 0000003F 00000040 0000007E 0000007F 00000080 00000081 00000082 00000083 00000084 00000085
Internal
detection
signal
In case of bit 6 detection
In case of bit 7 detection
AD
activation
trigger
Figure 11.19 Interval Timer Function
11.3.8 Twin-Capture Function
Channel 0 input capture register ICR0A, channel 1 offset base register 1 (OSBR1), and channel 2 offset base register 2
(OSBR2) can be made to perform input capture in response to the same trigger by means of a setting in timer I/O control
register 0 (TIOR0).
When TCNT0, TCNT1A, and TCNT2A in channel 0, channel 1, and channel 2 are started by a setting in the timer start
register (TSTR), and an edge of TI0A input (a trigger signal) is detected, the TCNT1A value is transferred to OSBR1, and
the TCNT2A value to OSBR2. Edge detection is as described in section 11.3.4, Input Capture Function.
An example of twin-capture operation is shown in figure 11.20.
Pφ
TCNT1A
Clock
TCNT1A 0000
0001
Edge detection signal
(from channel 0)
0002
0003
0004
0005
5678
5679
567A
567B
567C
567D
567E
OSBR1
0003
567A
Figure 11.20 Twin-Capture Operation
Rev.3.00 Mar. 12, 2008 Page 289 of 948
REJ09B0177-0300