SH7059 Datasheet, PDF (552/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.6 Timer Registers
The timer is a new function for the HCAN-II. The timer is 16 bits and supports several clock sources. It is divided by a
prescale counter to reduce the clock speed. It also supports two input capture registers (ICR1 and ICR0) and three compare
match registers (TCMR2, TCMR1, and TCMR0). The address map is as follows.
Note: These registers can only be accessed in word size (16 bits).
Table 17.7 HCAN Timer Registers
Channel Address (Bytes) Register Name
Abbreviation
Access Size (Bits)
0
H'D080
Timer counter register 0
TCNTR0
16
H'D082
Timer control register_0
TCR_0
16
H'D084
Timer status register_0
TSR_0
16
H'D086
Timer drift correction register 0
TDCR0
16
H'D088
Local offset register 0
LOSR0
16
H'D08A
Input capture register for cycle counter 0 ICR0-cc0
16
H'D08C
Input capture register for timer counter 0 ICR0-tm0
16
H'D08E
Input capture register 1_0
ICR1_0
16
H'D090
Timer compare match register 0_0
TCMR0_0
16
H'D092
Timer compare match register 1_0
TCMR1_0
16
H'D094
Timer compare match register 2_0
TCMR2_0
16
H'D096
Cycle counter register 0
CCR0
16
H'D098
Cycle maximum register 0
CMAX0
16
H'D09A
Timer mode register_0
TMR_0
16
H'D09C
Cycle counter double buffer 0
CCR_buf0
16
H'D09E
Input capture double buffer 0
ICR0_buf0
16
1
H'D880
Timer counter register 1
TCNTR1
16
H'D882
Timer control register_1
TCR_1
16
H'D884
Timer status register_1
TSR_1
16
H'D886
Timer drift correction register 1
TDCR1
16
H'D8D8
Local offset register 1
LOSR1
16
H'D88A
Input capture register for cycle counter 1 ICR0-cc1
16
H'D88C
Input capture register for timer counter 1 ICR0-tm1
16
H'D88E
Input capture register 1_1
ICR1_1
16
H'D890
Timer compare match register 0_1
TCMR0_1
16
H'D892
Timer compare match register 1_1
TCMR1_1
16
H'D894
Timer compare match register 2_1
TCMR2_1
16
H'D896
Cycle counter register 1
CCR1
16
H'D898
Cycle maximum register 1
CMAX1
16
H'D89A
Timer mode register_1
TMR_1
16
H'D89C
Cycle counter double buffer 1
CCR_buf1
16
H'D89E
Input capture double buffer 1
ICR0_buf1
16
Note: It is recommended that the timer should be disabled (TCR15 = 0) to change the setting of the registers related to the
timer.
Rev.3.00 Mar. 12, 2008 Page 462 of 948
REJ09B0177-0300