SH7059 Datasheet, PDF (305/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 4—Overflow Flag 3 (OVF3): Status flag that indicates TCNT3 input capture or compare-match.
Bit 4: OVF3
0
1
Description
[Clearing condition]
When OVF3 is read while set to 1, then 0 is written to OVF3
[Setting condition]
When the TCNT3 value overflows (from H'FFFF to H'0000)
(Initial value)
• Bit 3—Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR3D input capture or compare-
match.
Bit 3: IMF3D
0
1
Description
[Clearing condition]
When IMF3D is read while set to 1, then 0 is written to IMF3D
(Initial value)
[Setting conditions]
• When the TCNT3 value is transferred to GR3D by an input capture signal while GR3D is
functioning as an input capture register. However, IMF3D is not set by input capture with
a channel 9 compare match as the trigger
• When TCNT3 = GR3D while GR3D is functioning as an output compare register
• When TCNT3 = GR3D while GR3D is functioning as a synchronous register in PWM
mode
• Bit 2—Input Capture/Compare-Match Flag 3C (IMF3C): Status flag that indicates GR3C input capture or compare-
match. The flag is not set in PWM mode.
Bit 2: IMF3C
0
1
Description
[Clearing condition]
When IMF3C is read while set to 1, then 0 is written to IMF3C
(Initial value)
[Setting conditions]
• When the TCNT3 value is transferred to GR3C by an input capture signal while GR3C is
functioning as an input capture register. However, IMF3C is not set by input capture with
a channel 9 compare match as the trigger
• When TCNT3 = GR3C while GR3C is functioning as an output compare register
• Bit 1—Input Capture/Compare-Match Flag 3B (IMF3B): Status flag that indicates GR3B input capture or compare-
match. The flag is not set in PWM mode.
Bit 1: IMF3B
0
1
Description
[Clearing condition]
When IMF3B is read while set to 1, then 0 is written to IMF3B
(Initial value)
[Setting conditions]
• When the TCNT3 value is transferred to GR3B by an input capture signal while GR3B is
functioning as an input capture register. However, IMF3B is not set by input capture with
a channel 9 compare match as the trigger
• When TCNT3 = GR3B while GR3B is functioning as an output compare register
Rev.3.00 Mar. 12, 2008 Page 215 of 948
REJ09B0177-0300