SH7059 Datasheet, PDF (504/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
Start
[1]
Initialization
[2]
Read TDRE in SSSR
No
TDRE = 1?
Yes
Write transmit data to SSTDR
TDRE automatically cleared to 0
Data transferd from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
[3]
Continuous data transmission? ^Yes
No
Read TEND in SSSR
No
TEND = 1?
Yes
Clear TEND to 0
[4]
Has the
1-bit-transfer period
No
elapsed?
Yes
Clear TE in SSER to 0
End transmission
[1] Initialization:
Specify the settings such as transmit
data format.
[2] Check the SSU state and write
transmit data:
Write transmit data to SSTDR after
reading and confirming that the TDRE bit
is 1. The TDRE bit is automaticallu cleared
to 0 and transmission is started by writing
data to SSTDR. When data is written to
SSTDR, transmission starts.
[3] Procedure for continuous data transmission:
To continue data transmission, confirm
that the TDRE bit is 1 meaning tha SSTDR
is ready to be written to. After that, data can
be written to SSTDR. The TDRE bit is
automatically cleared to 0 by writing data to
SSTDR.
[4] Procedure to end data transmission:
To end data transmission, clear the TE bit to 0
once transmission of the last bit is complete.
Note: Hatching boxes represent SSU internal operations.
Figure 16.6 Example of Data Transmission Flowchart
• Data Reception
Figure 16.7 shows an example of reception operation, and figure 16.8 shows an example of data reception flowchart.
When receiving data, the SSU operates as shown below.
After the SSU sets the RE bit to 1 and dummy-reads SSRDR, data reception is started.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the received data is stored in SSRDR. At this
time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading
SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This
indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is
set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0.
Rev.3.00 Mar. 12, 2008 Page 414 of 948
REJ09B0177-0300