SH7059 Datasheet, PDF (45/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
23.6.1 Hardware Protection
881
Programming and erasing of flash memory is forcibly
disabled or suspended by hardware protection. In this
state, the downloading of an on-chip program and
initialization of the flash memory are possible.
23.6.3 Error Protection
Figure 23.16 Transitions to and from Error Protection State
883, 884
• When the relevant bank area of flash memory is read
during programming/erasing (including a vector read or
an instruction fetch)
• When a SLEEP instruction (including software standby
mode) is executed during programming/erasing
SH7058S/SH7059
24.6.1 Hardware Protection
Description amended
Programming and erasing of flash memory is forcibly
disabled or suspended by hardware protection. In this state
by the FWE pin, the downloading of an on-chip program
and initialization of the flash memory are possible.
24.6.3 Error Protection
Figure 24.16 Transitions to and from Error Protection State
Description amended
• Flash memory is read during programming/erasing
(including a vector read or an instruction fetch)
• When a SLEEP instruction is executed during
programming/erasing
…Note that the reset signal should only be released after
providing a reset input over a period longer than the normal
100 μs.
…Note that the reset signal should only be released after
providing a reset input over a period longer than the normal
100 μs.
Figure amended
Program mode
Erase mode
RES = 0 or HSTBY = 0
Reset or standby
(Hardware protection)
Read disabled
Programming/erasing
enabled
FLER=0
Error occurred
Er(rSorofotwccaurerresdtand_{RbEy)SH=0SToBr Y=0}
Read enabled
Programming/erasing disabled
FLER=0
RES=0 or
HSTBY=0
Programming/erasing interface
register is in its initial state.
Error protection mode Software standby mode
Error protection mode
(Software standby)
Read enabled
Programming/erasing disabled
FLER=1
Cancel
Read disabled
Programming/erasing disabled
software standby mode
FLER=1
Programming/erasing interface
register is in its initial state.
23.7 Flash Memory Emulation in RAM
Figure 23.18 Example of Overlapped RAM Operation
886
EB0 to EB15
H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
…
H'FFFFF
Program mode
Erase mode
Read disabled
Programming/erasing
enabled
FLER=0
Error occurred
RES = 0 or HSTBY = 0
Reset or standby
(Hardware protection)
Er(rSorofotwccaurerresdtand_{RbEy)SH=0SToBr Y=0}
Read enabled
Programming/erasing disabled
FLER=0
RES=0 ,
HSTBY=0
Programming/erasing interface
register is in its initial state.
or software standby mode cancellation
Error protection mode Software standby mode
(Software standby)
Read enabled
Programming/erasing disabled
FLER=1
Read disabled
Programming/erasing disabled
FLER=undefined
The power is not supplied in this LSI.
24.7 Flash Memory Emulation in RAM
Figure 24.18 Example of Overlapped RAM Operation
Address amended
EB0 to EB15
H'000000
H'001000
H'002000
H'003000
H'004000
H'005000
H'006000
H'007000
H'008000
…
H'0FFFFF
Rev.3.00 Mar. 12, 2008 Page xlv of xc
REJ09B0177-0300