SH7059 Datasheet, PDF (190/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. User Break Controller (UBC)
8.2.2 User Break Address Mask Register (UBAMR)
UBAMRH:
Bit:
Initial value:
R/W:
15
UBM31
0
R/W
14
UBM30
0
R/W
13
UBM29
0
R/W
12
UBM28
0
R/W
11
UBM27
0
R/W
10
UBM26
0
R/W
9
UBM25
0
R/W
8
UBM24
0
R/W
Bit:
Initial value:
R/W:
7
UBM23
0
R/W
6
UBM22
0
R/W
5
UBM21
0
R/W
4
UBM20
0
R/W
3
UBM19
0
R/W
2
UBM18
0
R/W
1
UBM17
0
R/W
0
UBM16
0
R/W
UBAMRL:
Bit:
Initial value:
R/W:
15
UBM15
0
R/W
14
UBM14
0
R/W
13
UBM13
0
R/W
12
UBM12
0
R/W
11
UBM11
0
R/W
10
UBM10
0
R/W
9
UBM9
0
R/W
8
UBM8
0
R/W
Bit:
Initial value:
R/W:
7
UBM7
0
R/W
6
UBM6
0
R/W
5
UBM5
0
R/W
4
UBM4
0
R/W
3
UBM3
0
R/W
2
UBM2
0
R/W
1
UBM1
0
R/W
0
UBM0
0
R/W
The user break address mask register (UBAMR) consists of user break address mask register H (UBAMRH) and user
break address mask register L (UBAMRL). Both are 16-bit readable/writable registers. UBAMRH designates whether to
mask any of the break address bits established in UBARH, and UBAMRL designates whether to mask any of the break
address bits established in UBARL. UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset, in module
standby mode, and in software standby mode.
• UBAMRH Bits 15 to 0—User Break Address Mask 31 to 16 (UBM31 to UBM16): These bits designate whether to
mask the corresponding break address 31 to 16 bits (UBA31 to UBA16) established in UBARH.
• UBAMRL Bits 15 to 0—User Break Address Mask 15 to 0 (UBM15 to UBM0): These bits designate whether to mask
the corresponding break address 15 to 0 bits (UBA15 to UBA0) established in UBARL.
Bits 15–0: UBMn
0
1
Note: n = 31 to 0
Description
Break address UBAn is included in the break conditions
Break address UBAn is not included in the break conditions
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 100 of 948
REJ09B0177-0300