SH7059 Datasheet, PDF (518/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 17.8, Usage
Notes.
Register
Name
Address
HCAN0
HCAN1
Data Bus
15 14 13 12 11 10 9 8 7 6
5
4
3
2
1
0
Access
Size
Field Name
MBx[0] to [1] H'100+N•32 H'900+N•32 0
STDID[10:0]
RTR IDE EXIDT[17:16] 16 bits
MBx[2] to [3] H'102+N•32 H'902+N•32
EXTID[15:0]
16 bits
Control
MBx[4] to [5] H'104+N•32 H'904+N•32 CCM TTE NMC ATX DART
MBC[2:0]
0 TCT CBE CLE
DLC[3:0]
8/16 bits
MBx[6] H'106+N•32 H'906+N•32
Timestamp[15:0]
16 bits Timestamp
MBx[7] to [8] H'108+N•32 H'908+N•32
MSG_DATA_0 (first Rx/Tx byte)
MSG_DATA_1
8/16 bits
MBx[9] to [10] H'10A+N•32 H'90A+N•32
MBx[11] to [12] H'10C+N•32 H'90C+N•32
MSG_DATA_2
MSG_DATA_4
MSG_DATA_3
MSG_DATA_5
8/16 bits
Data
8/16 bits
MBx[13] to [14] H'10E+N•32 H'90E+N•32
MSG_DATA_6
MSG_DATA_7
8/16 bits
MBx[15] to [16] H'110+N•32 H'910+N•32
MBx[17] to [18] H'112+N•32 H'912+N•32
Local acceptance filter mask 0 (LAFM0)/Tx trigger time 0 (TTT0)
Local acceptance filter mask 1 (LAFM1)/Tx trigger time 1 (TTT1)
16 bits
16 bits
LAFM/Tx
trigger
control
Notes: 1. All bits shadowed in gray are reserved and the write value should be 0. Values read out in the initial state are not guaranteed.
2. ATX, DART, and CLE are not supported by mailbox 0 and the MBC setting of mailbox 0 is limited.
3. If the CAN bus is configured in little endian (MCR4 = 1), transmission is started from MSG_DATA_1 instead of MSG_DATA_0
(i.e. the sequence becomes: MSG_DATA_1, MSG_DATA_0, MSG_DATA_3, MSG_DATA_2, MSG_DATA_5, MSG_DATA_4, MSG_DATA_7, and MSG_DATA_6).
4. x/N: 0 to 31 (indicates the mailbox number)
Figure 17.3 Mailbox-N Configuration
17.3.2 Message Control Field
Register Name Address
Bit
Bit Name Description
MBx[0], MBx[1]* H'100 + N • 32 15
⎯
Reserved
The write value should be 0. The read value is not guaranteed.
14 to 4 STDID [10:0] Standard ID
Set the ID (standard ID) of data frames and remote frames.
3
RTR
Remote Transmission Request
Distinguishes between data frames and remote frames. This bit
is overwritten by receive CAN frames depending on data frames
or remote frames.
Important: Note that, when the ATX bit is set with the setting
MBC = 001 the RTR bit cannot be set. When a remote frame is
received, the host CPU can be notified by the corresponding
RFPR or IRR2 (remote frame request interrupt), however, as the
HCAN needs to transmit the current message as a data frame,
the RTR bit remains 0.
0: Data frame
1: Remote frame
2
IDE
ID Extension
Distinguishes between the standard format and extended format
of CAN data frames and remote frames.
0: Standard format
1: Extended format
Rev.3.00 Mar. 12, 2008 Page 428 of 948
REJ09B0177-0300