SH7059 Datasheet, PDF (324/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 2—Input Capture/Compare-Match Interrupt Enable 3C (IME3C): Enables or disables interrupt requests by IMF3C
in TSR3 when IMF3C is set to 1.
Bit 2: IME3C
0
1
Description
IMI3C interrupt requested by IMF3C is disabled
IMI3C interrupt requested by IMF3C is enabled
(Initial value)
• Bit 1—Input Capture/Compare-Match Interrupt Enable 3B (IME3B): Enables or disables interrupt requests by IMF3B
in TSR3 when IMF3B is set to 1.
Bit 1: IME3B
0
1
Description
IMI3B interrupt requested by IMF3B is disabled
IMI3B interrupt requested by IMF3B is enabled
(Initial value)
• Bit 0—Input Capture/Compare-Match Interrupt Enable 3A (IME3A): Enables or disables interrupt requests by IMF3A
in TSR3 when IMF3A is set to 1.
Bit 0: IME3A
0
1
Description
IMI3A interrupt requested by IMF3A is disabled
IMI3A interrupt requested by IMF3A is enabled
(Initial value)
Timer Interrupt Enable Registers 6 and 7 (TIER6, TIER7)
TIER6 and TIER7 control enabling/disabling of channel 6 and 7 cycle register compare interrupt requests.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
CMExD CMExC CMExB CMExA
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R/W
R/W
R/W
R/W
Note: x = 6 or 7
• Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 3—Cycle Register Compare-Match Interrupt Enable 6D/7D (CME6D/CME7D): Enables or disables interrupt
requests by CMFxD in TSR6 or TSR7 when CMFxD is set to 1. Setting the DMAC while interrupt requests are
enabled allows the DMAC to be activated by an interrupt request.
Bit 3: CMExD
0
1
Note: x = 6 or 7
Description
CMIxD interrupt requested by CMFxD is disabled
CMIxD interrupt requested by CMFxD is enabled
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 234 of 948
REJ09B0177-0300