SH7059 Datasheet, PDF (117/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
2.1.3 System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the
procedure register (PR), and the program counter (PC). The multiply-and-accumulate registers store the results of
multiply-and-accumulate operations. The procedure register stores the return address from a subroutine procedure. The
program counter stores program addresses to control the flow of the processing. Figure 2.3 shows the system registers.
31
MACH
MACL
0 _{Multiply-and-accumulate (MAC)}
registers high and low (MACH,
MACL): Store the results of
multiply-and-accumulate operations.
31
PR
0 Procedure register (PR): Stores
the return address from a
subroutine procedure.
31
PC
0 _{Program counter (PC): Indicates}
the fourth byte (second instruction)
after the current instruction.
Figure 2.3 System Register Configuration
2.1.4 Floating-Point Registers
There are sixteen 32-bit floating-point registers, designated FR0 to FR15, which are used by floating-point instructions.
FR0 functions as the index register for the FMAC instruction. These registers are incorporated into the floating-point unit
(FPU). For details, see section 3, Floating-Point Unit (FPU).
31
FR0
FR1
0
FR0 functions as the index register
for the FMAC instruction.
FR2
FR3
FR4
FR5
FR6
FR7
FR8
FR9
FR10
FR11
FR12
FR13
FR14
FR15
Figure 2.4 Floating-Point Registers
Rev.3.00 Mar. 12, 2008 Page 27 of 948
REJ09B0177-0300