SH7059 Datasheet, PDF (615/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
When multi-trigger A/D conversion B ends, setting TADFxB to 1, a trigger A/D interrupt for A/D0 or A/D1 (TADIxB) is
requested if TADExB is 1. TADIxB can be cleared to 0 by clearing TADFxB or TADExB to 0.
• Bit 5—Trigger A/D Interrupt Enable A (TADExA): Enables or disables the interrupt request by TADFxA when the
trigger A/D flag xA (TADFxA) in ADTSR is set to 1.
To prevent incorrect operation, ensure that the ADTRG bit in A/D trigger interrupt enable register (ADTIER0 or
ADTIER1) is 0 before switching this setting.
Bit 5: TADExA
0
1
Description
The interrupt request (TADIxA) by TADFxA is disabled
The interrupt request (TADIxA) by TADFxA is enabled
(Initial value)
When multi-trigger A/D conversion A ends setting TADFxA to 1, a trigger A/D interrupt for A/D0 or A/D1 (TADIxA) is
requested if TADExA is 1. TADIxA can be cleared to 0 by clearing TADFxA or TADExA to 0.
• Bit 4—A/D Duty Interrupt Enable B (ADDExB): Enables or disables the interrupt request by ADDFxB when the
ADDRxB compare match flag (ADDFxB) in ADTSR is set to 1.
Bit 4: ADDExB
0
1
Note: x = 0 or 1.
Description
The interrupt request (ADDIxB) by ADDFxB is disabled
The interrupt request (ADDIxB) by ADDFxB is enabled
(Initial value)
• Bit 3—A/D Duty Interrupt Enable A (ADDExA): Enables or disables the interrupt request by ADDFxA when the
ADDRxA compare match flag (ADDFxA) in ADTSR is set to 1.
Bit 3: ADDExA
0
1
Note: x = 0 or 1.
Description
The interrupt request (ADDIxA) by ADDFxA is disabled
The interrupt request (ADDIxA) by ADDFxA is enabled
(Initial value)
• Bit 2—A/D Cycle Interrupt Enable (ADCYLEx): Enables or disables the interrupt request by ADCYLFx when the
A/D cycle compare match flow flag (ADCYLFx) in ADTSRx is set to 1.
Bit 2: ADCYLEx
0
1
Note: x = 0 or 1.
Description
The interrupt request (ADCYIx) by ADCYLFx is disabled
The interrupt request (ADCYIx) by ADCYLFx is enabled
(Initial value)
• Bit 1—A/D Compare Match Interrupt Enable B (ADCMExB): Enables or disables the interrupt request by ADCMFxB
when the ADDRxB compare match flag (ADCMFxB) in ADTSR is set to 1.
Bit 1: ADCMExB
0
1
Note: x = 0 or 1.
Description
The interrupt request (ADDIxB) by ADCMFxB is disabled
The interrupt request (ADDIxB) by ADCMFxB is enabled
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 525 of 948
REJ09B0177-0300