SH7059 Datasheet, PDF (215/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CK
Address
T₁
T₂
T_idle
T₁
9. Bus State Controller (BSC)
T₂
,
Data
CSn space access
Idle cycle
CSn space access
Figure 9.8 Same Space Consecutive Access Idle Cycle Insertion Example
9.5 Bus Arbitration
This LSI has a bus arbitration function that, when a bus release request is received from an external device, releases the
bus to that device. It also has three internal bus masters, the CPU, DMAC, and AUD. The priority ranking for determining
bus right transfer between these bus masters is:
Bus right request from external device > AUD > DMAC > CPU
Therefore, an external device that generates a bus request is given priority even if the request is made during a DMAC
burst transfer.
The AUD does not acquire the bus during DMAC burst transfer, but at the end of the transfer. When the CPU has
possession of the bus, the AUD has higher priority than the DMAC for bus acquisition.
A bus request by an external device should be input at the BREQ pin. The signal indicating that the bus has been released
is output from the BACK pin.
Figure 9.9 shows the bus right release procedure.
Rev.3.00 Mar. 12, 2008 Page 125 of 948
REJ09B0177-0300