SH7059 Datasheet, PDF (380/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.3.9 PWM Timer Function
Channels 6 and 7 can be used unconditionally as PWM timers using external pins (TO6A to TO6D, TO7A to TO7D).
In channels 6 and 7, when the corresponding bit is set in the timer start register (TSTR) and the free-running counter
(TCNT) is started, the counter counts up until its value matches the corresponding cycle register (CYLR). When TCNT
matches CYLR, it is cleared to H'0001 and starts counting up again from that value. At this time, 1 is output from the
corresponding external pin. An interrupt request can be sent to the CPU by setting the corresponding bit in the timer
interrupt enable register (TIER). If a value has been set in the duty register (DTR), when TCNT matches DTR, 0 is output
to the corresponding external pin. If the DTR value is H'0000, the output does not change (0% duty). To set H'0000 to
DTR, not write H'0000 directly to DTR but set H'0000 to BFR and then transfer the value to DTR. Writing H'0000 directly
to DTR may not give a duty of 0%. A duty of 100% is specified by setting DTR = CYLR. Do not set a value in DTR that
will result in the condition DTR > CYLR.
Channels 6 and 7 have buffers (BFR); the BFR value is transferred to DTR when TCNT matches CYLR. The duty value
written into BFR is reflected in the output value in the cycle following that in which BFR is written to.
An example of PWM timer operation is shown in figure 11.21.
In the example in figure 11.21, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0000 (0%), H'0004 (100%), and
H'0001 in BFR6A.
Pφ
STR6A
TCNT6A
Clock
TCNT6A ^{0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003}
CYLR6A
Write to
BFR6A
Data = 0000
0004
Data = 0004
Data = 0001
BFR6A
0002
0000
0004
0001
DTR6A
TO6A
*
PWM output does not change
for one cycle after activation
TSR6
CMF6A
Cycle
0002
0000
0004
0001
Cleared by software
Cleared by software
Cleared by software
Cycle
Cycle
Duty = 0%
Cycle
Duty = 100%
Cycle
Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation.
Figure 11.21 PWM Timer Operation
Channel 6 can be used in complementary PWM mode by making a setting in the PWM mode control register (PMDR).
On-duty or off-duty can also be selected with a setting in PMDR.
When TCNT6 is started by a setting in TSTR, it starts counting up. When TCNT6 reaches the CYLR6 value, it starts
counting down, and on reaching H'000, starts counting up again. The counter status is shown by TSR6. When TCNT6
underflows, an interrupt request can be sent to the CPU by setting the corresponding bit in TIER. When TCNT6 matches
the duty register (DTR6) value, the output is inverted. The output prior to the match depends on the PMDR setting. When
Rev.3.00 Mar. 12, 2008 Page 290 of 948
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