SH7059 Datasheet, PDF (328/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 2—One-Shot Pulse Interrupt Enable 8C (OSE8C): Enables or disables interrupt requests by OSF8C in TSR8 when
OSF8C is set to 1.
Bit 2: OSE8C
0
1
Description
OSI8C interrupt requested by OSF8C is disabled
OSI8C interrupt requested by OSF8C is enabled
(Initial value)
• Bit 1—One-Shot Pulse Interrupt Enable 8B (OSE8B): Enables or disables interrupt requests by OSF8B in TSR8 when
OSF8B is set to 1.
Bit 1: OSE8B
0
1
Description
OSI8B interrupt requested by OSF8B is disabled
OSI8B interrupt requested by OSF8B is enabled
(Initial value)
• Bit 0—One-Shot Pulse Interrupt Enable 8A (OSE8A): Enables or disables interrupt requests by OSF8A in TSR8 when
OSF8A is set to 1.
Bit 0: OSE8A
0
1
Description
OSI8A interrupt requested by OSF8A is disabled
OSI8A interrupt requested by OSF8A is enabled
(Initial value)
Timer Interrupt Enable Register 9 (TIER9)
TIER9 controls enabling/disabling of channel 9 event counter compare-match interrupt requests.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
—
Initial value:
0
R/W:
R
6
5
4
3
2
1
0
—
CME9F CME9E CME9D CME9C CME9B CME9A
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
• Bits 15 to 6—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 5—Compare-Match Interrupt Enable 9F (CME9F): Enables or disables interrupt requests by CMF9F in TSR9
when CMF9F is set to 1.
Bit 5: CME9F
0
1
Description
CMI9F interrupt requested by CMF9F is disabled
CMI9F interrupt requested by CMF9F is enabled
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 238 of 948
REJ09B0177-0300