SH7059 Datasheet, PDF (391/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CK
TCNT input clock
11. Advanced Timer Unit-II (ATU-II)
TCNT
N
N+1
GR (OCR, CYLR)
N
Compare-match signal
Interrupt status flag
IMF (CMF)
Interrupt request signal
IMI (CMI)
Figure 11.38 IMF (CMF) Setting Timing in Compare-Match
OVF Setting Timing in Overflow: When TCNT overflows (from H'FFFF to H'0000, or from H'FFFFFFFF to
H'00000000), the OVF bit is set to 1 in the timer status register (TSR).
The timing in this case is shown in figure 11.39.
CK
TCNT input clock
TCNT ^H'FFFF
Overflow signal
H'0000
Interrupt status flag
OVF
Interrupt request signal
OVI
Figure 11.39 OVF Setting Timing in Overflow
Rev.3.00 Mar. 12, 2008 Page 301 of 948
REJ09B0177-0300