SH7059 Datasheet, PDF (407/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Contention between TCNT Write and Counter Clearing by Overflow: With channel 0 to 5 and 11 free-running
counters (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT11), if overflow occurs in the T2
state of a CPU write cycle, the write to TCNT has priority and TCNT is not cleared.
Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as for normal overflow.
The timing in this case is shown in figure 11.66. In this example, H'5555 is written at the point at which TCNT overflows.
T1
T2
P
TCNT input clock
Address
TCNT address
Internal write signal
Overflow signal
TCNT
FFFF
5555
(CPU write value)
5556
Interrupt status flag
(OVF)
Figure 11.66 Contention between TCNT Write and Overflow
Rev.3.00 Mar. 12, 2008 Page 317 of 948
REJ09B0177-0300