SH7059 Datasheet, PDF (385/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Pφ
TSTR1
STR10
TCNT10A
Clock
TCNT10A
00000001
AGCK
Capture
transfer
signal
TCNT reset
signal
ICR10A
TSR10
IMF10A
OCR10A
TSR10
CMF10A
00000002
00000003
12345677
1234
5678
00000001
55555555
55555556
55555557
00000000
12345678
Cleared by software
55555556
Cleared by software
Figure 11.28 TCNT10A Capture Operation and Compare-Match Operation
Internally synchronized AGCK is counted by event count 10B (TCNT10B), and when TCNT10B reaches the value set
beforehand in compare-match register 10B (OCR10B), a compare-match occurs, and the compare-match trigger signal is
transmitted to channel 0. By setting the corresponding bit in TIER, an interrupt request can be sent to the CPU.
Figure 11.29 shows TCNT10B compare-match operation.
Pφ
AGCK
TCNT10B
Clock
TCNT10B
00
01
OCR10B
TSR10
CMF10B
Channel 0
trigger
55
56
55
Cleared by software
Figure 11.29 TCNT10B Compare-Match Operation
Multiplied Clock Generation Function: The channel 10 16-bit reload counter (TCNT10C, RLD10C) and 16-bit free-
running counter 10G (TCNT10G) can be used to multiply the interval between edges input from external pin TI10 by 32,
64, 128, or 256.
The value captured in ICR10A above is multiplied by 1/32, 1/64, 1/128, or 1/256 according to the value set in the timer
I/O control register (TIOR10), and transferred to the reload buffer (RLD10C). At the same time, the same value is
transferred to 16-bit reload counter 10C (TCNT10C) and a down-count operation is started. When this counter reaches
H'0001, the value is read automatically from RLD10C and the down-count operation is repeated. When this reload occurs,
a multiplied clock signal (AGCK1) is generated. AGCK1 is converted to a corrected clock (AGCKM) by the multiplied
clock correction function described in the following section.
Rev.3.00 Mar. 12, 2008 Page 295 of 948
REJ09B0177-0300