SH7059 Datasheet, PDF (30/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
21.1 Overview
Table 21.1 SH7058 Multiplex Pins
739 - 741, 743
Function 1
(Related Module)
Function 2
(Related Module)
PA14 input/output (port) TxD0 output (SCI)
PA15 input/output (port) RxD0 input (SCI)
PB13 input/output (port) SCK0 input/output (SCI)
PB15 input/output (port) PULS5 output (APC)
PC2 input/output (port) TxD2 output (SCI)
PC3 input/output (port) RxD2 input (SCI)
PF14 input/output (port) BACK output (BSC)
PF15 input/output (port) BREQ input (BSC)
PL7 input/output (port)
PL12 input/output (port)
PL13 input/output (port)
SCK2 input/output (SCI)
IRQ4 input (INTC)
IRQOUT output (INTC)
Function 3
(Related Module)
Function 4
(Related Module)
SCK2 input/output (SCI)
IRQOUT output (INTC)
SH7058S/SH7059
22.1 Overview
Table 22.1 SH7059 Multiplex Pins
Table amended
Function 1
(Related Module)
PA14 input/output (port)
PA15 input/output (port)
PB13 input/output (port)
PB15 input/output (port)
PC2 input/output (port)
PC3 input/output (port)
PF14 input/output (port)
PF15 input/output (port)
PL7 input/output (port)
PL12 input/output (port)
PL13 input/output (port)
Function 2
(Related Module)
TxD0 output (SCI)
RxD0 input (SCI)
SCK0 input/output (SCI)
PULS5 output (APC)
TxD2 output (SCI)
RxD2 input (SCI)
BACK output (BSC)
BREQ input (BSC)
SCK2 input/output (SCI)
IRQ4 input (INTC)
IRQOUT output (INTC)
Function 3
(Related Module)
SSO0 output (SSU)
SSI0 input (SSU)
SSCK0 output (SSU)
SCK2 input/output (SCI)
SSO1 output (SSU)
SSI1 input (SSU)
SCS0 input/output (SSU)
SCS1 input/output (SSU)
SSCK1 output (SSU)
SCS0 input/output (SSU)
IRQOUT output (INTC)
Function 4
(Related Module)
SSCK1 output (SSU)
SCS1 input/output (SSU)
21.3.1 Port A IO Register (PAIOR)
745
22.3.1 Port A IO Register (PAIOR)
Description amended
Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0
to PA0/TI0A. PAIOR is enabled when port A pins function
as general input/output pins (PA15 to PA0) or ATU-II
input/output pins, and disabled otherwise.
…When port A pins function as PA15 to PA0 or ATU-II
input/output pins, a pin becomes an output when the
corresponding bit in PAIOR is set to 1, and an input when
the bit is cleared to 0.
Bits PA15IOR to PA0IOR correspond to pins
PA15/RxD0/SSI0 to PA0/TI0A. PAIOR is enabled when
port A pins function as general input/output pins (PA15 to
PA0), ATU-II input/output pins or transmit/receive
input/output for the SSU (SSI0 and SSO0), and disabled
otherwise.
…When port A pins function as PA15 to PA0, ATU-II
input/output pins or transmit/receive input/output for the
SSU (SSI0 and SSO0), a pin becomes an output when the
corresponding bit in PAIOR is set to 1, and an input when
the bit is cleared to 0.
PAIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
PAIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
21.3.2 Port A Control Registers H and L (PACRH, PACRL)
746
PACRH and PACRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), and in hardware
standby mode. They are not initialized in software standby
mode or sleep mode.
22.3.2 Port A Control Registers H and L (PACRH, PACRL)
Description amended
PACRH and PACRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), in hardware
standby mode, and in software standby mode. They are
not initialized in sleep mode.
Rev.3.00 Mar. 12, 2008 Page xxx of xc
REJ09B0177-0300