SH7059 Datasheet, PDF (37/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
21.3.23 Port L IO Register (PLIOR)
796
Bits PL13IOR to PL0IOR correspond to pins PL13/IRQOUT
to PL0/TI10. PLIOR is enabled when port L pins function as
general input/output pins (PL13 to PL0), timer input/output
pins (TIO11A, TIO11B), or serial clock pins (SCK2, SCK3,
SCK4), and disabled otherwise.
When port L pins function as PL13 to PL0, TIO11A and
TIO11B, or SCK2, SCK3, and SCK4, a pin becomes an
output when the corresponding bit in PLIOR is set to 1, and
an input when the bit is cleared to 0.
PLIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.3.23 Port L IO Register (PLIOR)
Description amended
Bits PL13IOR to PL0IOR correspond to pins
PL13/IRQOUT/SCS1 to PL0/TI10. PLIOR is enabled when
port L pins function as general input/output pins (PL13 to
PL0), timer input/output pins (TIO11A, TIO11B), or serial
clock pins (SCK2, SCK3, SCK4, SSCK1), and disabled
otherwise.
When port L pins function as PL13 to PL0, TIO11A and
TIO11B, or SCK2, SCK3, SCK4, and SSCK1 a pin
becomes an output when the corresponding bit in PLIOR is
set to 1, and an input when the bit is cleared to 0.
PLIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
21.3.24 Port L Control Registers H and L (PLCRH, PLCRL)
Port L Control Register H (PLCRH)
797, 798
PLCRH and PLCRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), and in hardware
standby mode. They are not initialized in software standby
mode or sleep mode.
22.3.24 Port L Control Registers H and L (PLCRH, PLCRL)
Port L Control Register H (PLCRH)
Description amended
PLCRH and PLCRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), in hardware
standby mode, and in software standby mode. They are
not initialized in sleep mode.
Bit: 15
9
8
Bit: 15
9
8
—
—
PL12
MD
—
PL12 PL12
MD1 MD0
Initial value: 0
0
0
Initial value: 0
0
0
R/W: R
R
R/W
R/W: R
R/W R/W
• Bits 11 and 10—PL13 Mode Bits 1 and 0 (PL13MD1,
PL13MD0): These bits select the function of pin
PL13/IRQOUT.
Bit 11: PL13MD1
0
1
Bit 10: PL13MD0
0
1
0
1
Description
General input/output (PL13)
(Initial value)
IRQOUT is fixed high (IRQOUT)
IRQOUT is output by INTC interrupt request
(IRQOUT)
Reserved (Do not set)
• Bits 11 and 10—PL13 Mode Bits 1 and 0 (PL13MD1,
PL13MD0): These bits select the function of pin
PL13/IRQOUT/SCS1.
Bit 11: PL13MD1
0
1
Bit 10: PL13MD0
0
1
0
1
Description
General input/output (PL13)
IRQOUT is fixed high (IRQOUT)
IRQOUT is output by INTC interrupt request (IRQOUT)
Chip select input/output (SCS1)
(Initial value)
• Bit 9—Reserved: This bit is always read as 0. The write
value should always be 0.
• Bit 8—PL12 Mode Bit (PL12MD): Selects the function
of pin PL12/IRQ4.
Bit 8: PL12MD
0
1
Description
General input/output (PL12)
Interrupt request input (IRQ4)
(Initial value)
• Bit 9, 8—PL12 Mode Bit 1,0 (PL12MD0,PL12MD0):
Selects the function of pin PL12/IRQ4/SCS0.
Bit 9: PL12MD1
0
1
Bit 8: PL12MD0
0
1
0
1
Description
General input/output (PL12)
Interrupt request input (IRQ4)
Chip select input/output (SCS0)
Reserved (Do not set)
(Initial value)
Rev.3.00 Mar. 12, 2008 Page xxxvii of xc
REJ09B0177-0300