SH7059 Datasheet, PDF (81/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14.4.2 Compare Match Flag Set Timing.............................................................................................................. 350
14.4.3 Compare Match Flag Clear Timing .......................................................................................................... 350
14.5 Usage Notes ........................................................................................................................................................... 351
14.5.1 Contention between CMCNT Write and Compare Match ........................................................................ 351
14.5.2 Contention between CMCNT Word Write and Incrementation................................................................ 351
14.5.3 Contention between CMCNT Byte Write and Incrementation ................................................................. 352
Section 15 Serial Communication Interface (SCI) ...........................................................................353
15.1 Overview................................................................................................................................................................ 353
15.1.1 Features..................................................................................................................................................... 353
15.1.2 Block Diagram .......................................................................................................................................... 354
15.1.3 Pin Configuration...................................................................................................................................... 355
15.1.4 Register Configuration.............................................................................................................................. 356
15.2 Register Descriptions ............................................................................................................................................. 357
15.2.1 Receive Shift Register (RSR) ................................................................................................................... 357
15.2.2 Receive Data Register (RDR) ................................................................................................................... 357
15.2.3 Transmit Shift Register (TSR) .................................................................................................................. 357
15.2.4 Transmit Data Register (TDR).................................................................................................................. 357
15.2.5 Serial Mode Register (SMR)..................................................................................................................... 358
15.2.6 Serial Control Register (SCR)................................................................................................................... 360
15.2.7 Serial Status Register (SSR) ..................................................................................................................... 362
15.2.8 Bit Rate Register (BRR) ........................................................................................................................... 365
15.2.9 Serial Direction Control Register (SDCR)................................................................................................ 370
15.2.10 Inversion of SCK Pin Signal..................................................................................................................... 370
15.3 Operation................................................................................................................................................................ 371
15.3.1 Overview................................................................................................................................................... 371
15.3.2 Operation in Asynchronous Mode ............................................................................................................ 373
15.3.3 Multiprocessor Communication................................................................................................................ 380
15.3.4 Synchronous Operation............................................................................................................................. 387
15.4 SCI Interrupt Sources and the DMAC ................................................................................................................... 393
15.5 Usage Notes ........................................................................................................................................................... 394
15.5.1 TDR Write and TDRE Flag ...................................................................................................................... 394
15.5.2 Simultaneous Multiple Receive Errors ..................................................................................................... 394
15.5.3 Break Detection and Processing (Asynchoronous Mode Only)................................................................ 395
15.5.4 Sending a Break Signal (Asynchoronous Mode Only) ............................................................................. 395
15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only) ............................................ 395
15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode......................................... 395
15.5.7 Constraints on DMAC Use ....................................................................................................................... 396
15.5.8 Cautions on Synchronous External Clock Mode ...................................................................................... 396
15.5.9 Caution on Synchronous Internal Clock Mode ......................................................................................... 396
15.5.10 Note on Writing to Registers During Transmit, Receive, and Transmit/Receive Operations................... 396
Section 16 Synchronous Serial Communication Unit (SSU) ...........................................................397
16.1 Features .................................................................................................................................................................. 397
16.2 Input/Output Pins ................................................................................................................................................... 399
16.3 Register Descriptions ............................................................................................................................................. 399
16.3.1 SS Control Register H (SSCRH)............................................................................................................... 401
16.3.2 SS Control Register L (SSCRL) ............................................................................................................... 402
16.3.3 SS Mode Register (SSMR) ....................................................................................................................... 403
16.3.4 SS Enable Register (SSER)....................................................................................................................... 404
16.3.5 SS Status Register (SSSR) ........................................................................................................................ 405
16.3.6 SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3) ........................................................................ 407
Rev.3.00 Mar. 12, 2008 Page lxxxi of xc
REJ09B0177-0300