SH7059 Datasheet, PDF (648/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. High-performance User Debug Interface (H-UDI)
TCK
TMS
TDI
TDO
TCK
TS0 TS3
SDTRF
Figure 20.4 Data Input/Output Timing Chart (2)
TMS
TDI
TDO
Bit
Bit
0
31
Bit
Bit
0
31
SDTRF
Bit
Bit
0
31
SDTRF
Bit
Bit
0
31
Figure 20.5 Data Input/Output Timing Chart (3)
20.4.3 H-UDI Reset
The H-UDI can be reset in the following cases.
• When the TRST signal is held at 0.
• When TRST = 1 and at least five TCK clock cycles are input while TMS = 1.
• When the MSTOP2 bit in SYSCR2 is set to 1 (see section 27.2.3).
• In hardware standby mode.
• In software standby mode.
Rev.3.00 Mar. 12, 2008 Page 558 of 948
REJ09B0177-0300