SH7059 Datasheet, PDF (202/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
9.1.5 Address Map
Figure 9.2 shows the address format used by this LSI.
A31–A24
A23, A22 A21
A0
Output address:
Output from the address pins
CS space selection:
Decoded, outputs to
when A31 to A24 = 00000000
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS0 to CS3 space when 00000000 (H'00)
Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 9.2 Address Format
This chip uses 32-bit addresses:
• Bits A31 to A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the corresponding areas when bits
A31 to A24 are 00000000.
• A21 to A0 are output externally.
Table 9.3 shows the address map.
Table 9.3 Address Map (SH7058S)
• On-chip ROM enabled mode
Address
H'0000 0000 to H'000F FFFF
H'0010 0000 to H'001F FFFF
H'0020 0000 to H'003F FFFF
H'0040 0000 to H'007F FFFF
H'0080 0000 to H'00BF FFFF
H'00C0 0000 to H'00FF FFFF
H'0100 0000 to H'FFFE FFFF
H'FFFF 0000 to H'FFFF BFFF
H'FFFF C000 to H'FFFF FFFF
Space
On-chip ROM
Reserved
CS0 space
CS1 space
CS2 space
CS3 space
Reserved
On-chip RAM
On-chip peripheral module
Memory
On-chip ROM
Reserved
External space
External space
External space
External space
Reserved
On-chip RAM
On-chip peripheral module
Size
1 MB
2 MB
4 MB
4 MB
4 MB
48 KB
16 KB
Bus Width
32 bits
8, 16 bits*¹
8, 16 bits*¹
8, 16 bits*¹
8, 16 bits*¹
32 bits
8, 16 bits
Rev.3.00 Mar. 12, 2008 Page 112 of 948
REJ09B0177-0300