SH7059 Datasheet, PDF (562/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
• ICR0_tm/ICR1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICR0_tm[15:0], ICR1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name Initial Value R/W Description
15 to 0 ICR0_tm[15: 0
0]
R/W* This register samples the value of the timer (TCNTR) at every SOF on the
CAN bus when enabled by TCR[14].
Note: * This register can be written to, however, the written value is ignored.
Bit
Bit Name Initial Value R/W Description
15 to 0 ICR1[15:0] 0
R/W* This register samples the value of the timer (TCNTR) at the condition
specified by bit 13 (for reception) and bit 12 (for transmission) in TCR.
Note: * This register can be written to, however, the written value is ignored.
17.6.11 Timer Compare Match Registers n (TCMR0n, TCMR1n, TCMR2n) (n = 0, 1)
• TCMR0, TCMR1, and TCMR
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCMR0[15:0], TCMR1[15:0], TCMR2[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
Bit Name Initial Value R/W
TCMR0[15:0] , 0
R/W
TCMR1[15:0],
TCMR2[15:0]
Description
The timer compare match registers (TCMR0, TCMR1, and TCMR2) are 16-
bit readable/writable registers that generate interrupt signals, clear/set the
timer value (only supported by TCMR0), or clear the transmit messages in
the queue (only supported by TCMR2). (These registers offer exactly the
same function except for the clear of the timer and the clear of the
transmission.) The value used for the compare can be set independently for
each register, using bits 1, 2, and 3 in TMR (timer mode register), to be the
timer value (TCNTR[15:0]) or the value of Cycle_Count + TCNTR[15:4].
Interrupts are flagged by bits 15, 14, and 11 in IRR when a compare match
occurs, and these bits cannot be prevented from being set in IRR except
when the TCMR value is H'0000. The generation of interrupt signals can be
masked by bits 15, 14, and 11 in IMR. When a compare match occurs and
IRR15 (or IRR14 or IRR11) is set, bits 2, 1, and 3 in TSR (HCAN timer status
register) are also set. Clearing the IRR bit also clears the corresponding bit
in TSR.
The timer value is cleared and LOSR is set when a compare match occurs to
TCMR0 if bit 11 in TCR is enabled (timer clear/set function). TCMR1 and
TCMR2 do not have this function.
The messages in the transmit queue are cleared only when a compare
match occurs to TCMR2 (cancellation of the messages in the transmit
queue). TCMR1 and TCMR0 do not have this function.
Important: TCMR0 and TCMR2 are not supported by this LSI. The setting
must be H'0000.
Rev.3.00 Mar. 12, 2008 Page 472 of 948
REJ09B0177-0300