SH7059 Datasheet, PDF (43/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
23.4.2 Programming/Erasing Interface Registers
847
The programming/erasing interface registers are as
described below. They are all 8-bit registers that can be
accessed in bytes. Except for the FLER bit in FCCS and
FMATS, these registers are initialized at a power-on reset,
in hardware standby mode, or in software standby mode.
The FLER bit or FMATS is not initialized in software
standby mode.
24.4.2 Programming/Erasing Interface Registers
Descritpion amended
The programming/erasing interface registers are as
described below. They are all 8-bit registers that can be
accessed in bytes. These regiseters are initialized at a
power-on reset, in hardware standby mode, or in software
standby mode.
• Bit 0—Source Program Copy Operation (SCO):
… Four NOP instructions must be executed immediately
after setting this bit to 1.
• Bit 0—Source Program Copy Operation (SCO):
… Eight NOP instructions must be executed immediately
after setting this bit to 1.
23.4.3 Programming/Erasing Interface Parameters
851
… This parameter uses the general registers of the CPU
(R4, R5, and R0) or the on-chip RAM area. The initial value
is undefined at a power-on reset or in hardware standby
mode.
24.4.3 Programming/Erasing Interface Parameters
Description amended
… This parameter uses the general registers of the CPU
(R4, R5, and R0) or the on-chip RAM area. The initial value
is undefined at a power-on reset, in hardware standby
mode, or in software standby mode.
(1) Download Control
852
… The on-chip RAM area to be downloaded is the area as
much as 2 kbytes starting from the start address specified
by FTDAR. For the address map of the on-chip RAM, see
figure 23.10.
(1) Download Control
Description amended
…The on-chip RAM area to be downloaded is the area as
much as 3 Kbytes starting from the start address specified
by FTDAR. For the address map of the on-chip RAM, see
figure 24.10.
23.4.4 RAM Emulation Register (RAMER)
862
… RAMER is initialized to H'0000 at a power-on reset or in
hardware standby mode and is not initialized in software
standby mode. The RAMER setting must be executed in
user mode or in user program mode.
24.4.4 RAM Emulation Register (RAMER)
Description amended
… RAMER is initialized to H'0000 at a power-on reset or in
hardware standby mode, or in software standby mode. The
RAMER setting must be executed in user mode or in user
program mode.
23.5.1 Boot Mode
864
…After the SCI bit rate is automatically adjusted, the
communication with the host is executed by means of the
control command method.
24.5.1 Boot Mode
Description added
… After the SCI bit rate is automatically adjusted, the
communication with the host is executed by means of the
control command method. The RAM areas used by boot
mode are 3 Kbytes starting at address H'FFFF0000, 4
Kbytes starting at address H'FFFFB000, and 128 bytes
from H'FFFFBF80 to H'FFFFBFFF, which are used as the
stack.
(1) SCI Interface Setting by Host
Table 23.8 System Clock Frequency that Can
Automatically Adjust Bit Rate of This LSI
865
(1) SCI Interface Setting by Host
Table 24.8 System Clock Frequency that Can
Automatically Adjust Bit Rate of This LSI
Table amended
Host Bit Rate
9,600 bps
19,200 bps
System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate
20 to 40 MHz (input frequency of 5 to 10 MHz)
20 to 40 MHz (input frequency of 5 to 10 MHz)
Host Bit Rate
9,600 bps
19,200 bps
System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate
40 to 80 MHz (input frequency of 5 to 10 MHz)
40 to 80 MHz (input frequency of 5 to 10 MHz)
Rev.3.00 Mar. 12, 2008 Page xliii of xc
REJ09B0177-0300