SH7059 Datasheet, PDF (546/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
15 to 0
Bit Name
TXACK1
[15:0]
Initial Value R/W Description
0
R/WC1 Notify that the requested transmission of the corresponding mailbox has
been finished successfully. Bits 15 to 0 correspond to mailboxes 31 to 16
respectively.
0: Clearing condition: Writing 1
1: Corresponding mailbox has successfully transmitted message
(data or remote frame)
Setting condition: Completion of message transmission for corresponding
mailbox
• TXACK0n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXACK0[15:1]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Bit
15 to 1
0
Bit Name Initial Value R/W Description
TXACK0[15: 0
1]
R/WC1 Notify that the requested transmission of the corresponding mailbox has
been finished successfully. Bits 15 to 1 correspond to mailboxes 15 to 1
respectively.
0: Clearing condition: Writing 1
1: Corresponding mailbox has successfully transmitted message
(data or remote frame)
Setting condition: Completion of message transmission for corresponding
mailbox
TXACK0[0] 0
R
Reserved
This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is
ignored. The read value is always 0.
17.5.4 Abort Acknowledge Register n (ABACK1n, ABACK0n) (n = 0, 1)
ABACK1 and ABACK0 are 16-bit readable/conditionally-writable registers. These registers notify the host CPU that a
mailbox transmission has been aborted as per its request. When an abort has succeeded, the HCAN sets the corresponding
bit in ABACK. The host CPU can clear the ABACK bit by writing 1 to the corresponding bit. Writing 0 is ignored. An
ABACK bit is used by the HCAN to acknowledge that a TXPR bit has been cleared by the corresponding TXCR bit.
• ABACK1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABACK1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Rev.3.00 Mar. 12, 2008 Page 456 of 948
REJ09B0177-0300