SH7059 Datasheet, PDF (177/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
Interrupt Vector
Interrupt Source
Vector
No.
Vector Table
Address
Offset
SCI0/
SSU0*
ERI0/ 200
SSERI0
H'00000320 to
H'00000323
RXI0/ 201
SSRXI0
H'00000324 to
H'00000327
TXI0/
202
SSTSI0
H'00000328 to
H'0000032B
TEI0
203
H'0000032C to
H'0000032F
SCI1
ERI1
204
H'00000330 to
H'00000333
RXI1
205
H'00000334 to
H'00000337
TXI1
206
H'00000338 to
H'0000033B
TEI1
207
H'0000033C to
H'0000033F
SCI2/
SSU1*
ERI2/ 208
SSERI1
H'00000340 to
H'00000343
RXI2/ 209
SSRXI1
H'00000344 to
H'00000347
TXI2/
210
SSTSI1
H'00000348 to
H'0000034B
TEI2
211
H'0000034C to
H'0000034F
SCI3
ERI3
212
H'00000350 to
H'00000353
RXI3
213
H'00000354 to
H'00000357
TXI3
214
H'00000358 to
H'0000035B
TEI3
215
H'0000035C to
H'0000035F
SCI4
ERI4
216
H'00000360 to
H'00000363
RXI4
217
H'00000364 to
H'00000367
TXI4
218
H'00000368 to
H'0000036B
TEI4
219
H'0000036C to
H'0000036F
Note: * SSU: Synchronous Serial Communication Unit
Interrupt
Priority
(Initial
Value)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
Corre-
sponding
IPR (Bits)
IPRK (15–12)
IPRK (11–8)
IPRK (7–4)
IPRK(3–0)
IPRL (15–12)
Priority
within IPR
Default
Setting Range Priority
↑
1
High
2
3
↓
4
↑
1
2
3
↓
4
↑
1
2
3
↓
4
↑
1
2
3
↓
4
↑
1
2
3
↓
4
Low
Rev.3.00 Mar. 12, 2008 Page 87 of 948
REJ09B0177-0300