SH7059 Datasheet, PDF (126/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Instruction Formats
nd4 format
15
xxxx xxxx
nnnn
0
dddd
Source
Operand
R0 (Direct register)
Destination
Operand
nnnndddd: Indirect
register with
displacement
Example
MOV.B R0,@(disp,Rn)
nmd format
15
0
xxxx nnnn mmmm dddd
d format
15
xxxx
xxxx
0
dddd dddd
d12 format
15
xxxx dddd
dddd
0
dddd
mmmm: Direct register
mmmmdddd: Indirect
register with displacement
dddddddd: Indirect GBR
with displacement
R0 (Direct register)
dddddddd: PC relative with
displacement
—
—
nnnndddd: Indirect
register with
displacement
nnnn: Direct register
MOV.L Rm,@(disp,Rn)
MOV.L @(disp,Rm),Rn
R0 (Direct register)
MOV.L @(disp,GBR),R0
dddddddd: Indirect
GBR with
displacement
R0 (Direct register)
MOV.L R0,@(disp,GBR)
MOVA @(disp,PC),R0
dddddddd: PC relative
dddddddddddd: PC
relative
BF
label
BRA label
(label = disp + PC)
nd8 format
15
xxxx nnnn
dddd
0
dddd
dddddddd: PC relative with nnnn: Direct register
displacement
MOV.L @(disp,PC),Rn
i format
15
0
xxxx xxxx i i i i i i i i
ni format
15
0
xxxx nnnn i i i i i i i i
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
Indirect indexed GBR
R0 (Direct register)
—
nnnn: Direct register
AND.B
AND
TRAPA
ADD
#imm,@(R0,GBR)
#imm,R0
#imm
#imm,Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev.3.00 Mar. 12, 2008 Page 36 of 948
REJ09B0177-0300