SH7059 Datasheet, PDF (25/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
16.7.9 DMAC Interface
Figure 16.13 DMAC Transfer Flowchart
608
SH7058S/SH7059
17.7.9 DMAC Interface
Figure 17.13 DMAC Transfer Flowchart
Figure amended
Initial setting of DMAC
Set activation source
Set source and destination addresses
Set number of transmissions and interrupts
: Processing by hardware
: Setting by user
Initial setting of DMAC
Set activation source
Set source and destination addresses
Set number of transmissions and interrupts
: Processing by hardware
: Setting by user
Receive a message at
mailbox 0 in channel 0
Receive a message at
mailbox 0 in channel 0
Activate DMAC
Activate DMAC
DMAC transfer ended?
Set DMAC transfer end bit
Clear RXPR and RFPR
No
DMAC transfer ended?
Yes
Set DMAC transfer end bit
Clear RXPR and RFPR
Enable DMAC interrupt
Interrupt to CPU
Enable DMAC interrupt
No
Yes
Interrupt to CPU
Clear DMAC interrupt flag
Clear DMAC interrupt flag
End
End
16.7.11 CAN Bus Interface
Figure 16.16 High-Speed Interface Using HA13721
610
17.1.1 Features
617
• High-speed conversion
Conversion time: minimum 13.3 µs per channel (when
peripheral clock (Pf) = 20 MHz)
17.1.4 Register Configuration
Table 17.2 A/D Converter Registers
624
Notes: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles.
1. A 16-bit access must be made on a word boundary.
2. Only 0 can be written to bit 7 to clear the flag.
17.4.3 Analog Input Sampling and A/D Conversion Time
Table 17.4 A/D Conversion Time (Single Mode)
644
CKS0 : Peripheral Clock (Pφ) = 10 to 20MHz
CKS1 : Peripheral Clock (Pφ) = 10MHz
17.7.11 CAN Bus Interface
Figure 17.16 Using the PCA82C250 in a High-Speed
Interface
Replaced due to the transceiver IC changed.
18.1.1 Features
Description amended
• High-speed conversion
Conversion time: minimum 13.3 µs per channel (when fop
= 20 MHz)
18.1.4 Register Configuration
Table 18.2 A/D Converter Registers
Notes amended
Notes: 1. A 16-bit access must be made on a word
boundary.
2. Only 0 can be written to bit 7 to clear the flag.
18.4.3 Analog Input Sampling and A/D Conversion Time
Table 18.4 A/D Conversion Time (Single Mode)
Table amended
CKS0 : fop = 10 to 20MHz
CKS1 : fop = 10MHz
States (peripheral clock (Pφ))
States (CK base)
Rev.3.00 Mar. 12, 2008 Page xxv of xc
REJ09B0177-0300