SH7059 Datasheet, PDF (276/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.2.3 Timer Control Registers (TCR)
The timer control registers (TCR) are 8-bit registers. The ATU-II has 16 TCR registers: two each for channels 1 and 2, one
each for channels 3, 4, 5, 8, and 11, two each for channels 6 and 7, and three for channel 9. For details of channel 10, see
section 11.2.26, Channel 10 Registers.
Channel
1
2
3
4
5
6
7
8
9
11
Abbreviation
TCR1A, TCR1B
TCR2A, TCR2B
TCR3
TCR4
TCR5
TCR6A, TCR6B
TCR7A, TCR7B
TCR8
TCR9A, TCR9B, TCR9C
TCR11
Function
Internal clock/external clock/TI10 input clock selection
Internal clock selection
External clock selection/setting of channel 3 trigger in event of compare-match
Internal clock/external clock selection
Each TCR is an 8-bit readable/writable register that selects whether an internal clock or external clock is used for channels
1 to 5 and 11. For channels 6 to 8, TCR selects an internal clock, and for channel 9, an external clock.
When an internal clock is selected, TCR selects the value of φ" further scaled from clock φ' scaled with prescaler register
(PSCR). Scaled clock φ" can be selected, for channels 1 to 8 and 11 only, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32 (only φ'
is available for channel 0). Edge detection is performed on the rising edge.
When an external clock is selected, TCR selects whether TCLKA, TCLKB (channels 1 to 5 and 11 only), TI10 pin input
(channels 1 to 5 only), or a TI10 pin input multiplied clock (channels 1 to 5 only) is used, and also performs edge
selection.
Each TCR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode.
Timer Control Registers 1A, 1B, 2A, 2B (TCR1A, TCR1B, TCR2A, TCR2B)
TCR1A, TCR2A
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
—
—
CKEGA1 CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
TCR1B, TCR2B
Bit:
7
—
Initial value:
0
R/W:
R
6
5
4
3
2
1
0
—
CKEGB1 CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
• Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0.
Rev.3.00 Mar. 12, 2008 Page 186 of 948
REJ09B0177-0300