SH7059 Datasheet, PDF (499/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Table 16.4 DATS Bit Settings and SSRDR Bit Status
SSRDR
0
1
2
3
DATS [1:0] (SSCRL [1:0])
00
01
Valid
Valid
Invalid
Valid
Invalid
Invalid
Invalid
Invalid
16. Synchronous Serial Communication Unit (SSU)
10
Valid
Valid
Valid
Valid
11 (Setting Invalid)
Invalid
Invalid
Invalid
Invalid
SSRDR is initialized by a power-on reset, hardware standby mode, and software standby mode. It is not initialized by a
manual reset.
16.3.8 SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data.
When data from SSTDR to SSTRSR is transferred with MLS = 0, bit 0 of transmit data is bit 0 in the SSTDR contents
(LSB first communication). When data from SSTDR to SSTRSR is transferred with MLS = 1, bit 0 of transmit data is bit
7 in the SSTDR contents (MSB first communication). To perform serial data transmission, the SSU transfers data starting
from LSB (bit 0) in SSTRSR to the SSO pin.
In reception, the SSU sets serial data that has been input from the SSI pin to SSTRSR starting from LSB (bit 0) and
converts it into parallel data. When 1-byte data has been received, the SSTRSR contents are automatically transferred to
SSRDR. SSTRSR cannot be directly accessed by the CPU.
Rev.3.00 Mar. 12, 2008 Page 409 of 948
REJ09B0177-0300