SH7059 Datasheet, PDF (618/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
19.3 Operation
19.3.1 Overview
The multi-trigger A/D converter is divided into the timer parts and A/D conversion parts. The timer parts include two
channels 0 and 1, each of which includes the prescaler that can generate or provide the selection of an input clock having
the desired frequency. The following are general descriptions of the operations of the channels and prescalers.
(1) Channels 0 and 1
Channels 0 and 1 include 16-bit free running counters (ADCNT0 and ADCNT1), 16-bit cycle registers (ADCYLR0
and ADCYLR1), 16-bit duty registers (ADDR0A, ADDR0B, ADDR1A, and ADDR1B), and 16-bit general registers
(ADGR0A, ADGR0B, ADGR1A, and ADGR1B), respectively. They also have external output pins of their own
(ADTO0A, ADTO0B, ADTO1A, and ADTO1B), thus allowing the channels to be used as PWM timers.
ADCNT0 and ADCNT1, which are the incrementing counters, output 0 (1)* to the external output pins when the
counter value matches the ADDR value (when ADDR ≠ ADCYLR). When the counter value matches the ADCYLR
value (when ADDR ≠ H'0000), ADCNT0 and ADCNT1 output 1 (0)* to the external output pins, simultaneously
clearing the ADCNT value to H'0001. Due to these operations, channels 0 and 1 can output a waveform having the
cycle specified by the ADCYLR value and the duty specified by the ADDR value.
When ADDR = ADCYLR, ADCNT0 and ADCNT1 output 1 (0)* continuously to the external output pins, thus
providing a 100%-duty waveform, and when ADDR = H'0000, these counters output 0 (1)* continuously to the
external output pins, thus providing a 0%-duty waveform. Note that the ADDR value should never be greater than the
ADCYLR value.
Channels 0 and 1 also perform the compare match operation when the ADCNT value matches the ADGR0A,
ADGR0B, ADGR1A, or ADGR1B value that has been set in ADGR previously. However, no output pins are
provided. The channels can also trigger multi-trigger A/D conversion using the compare matches. Neither ADCNT0
nor ADCNT1 is cleared when the value matches the ADGR0A, ADGR0B, ADGR1A, or ADGR1B value.
Note: * Selected by the A/D trigger control register (ADTCR).
(2) Prescalers
The channels incorporate dedicated prescalers, which can halt the clock signal that is input from the first stage or
divide the frequency of the clock signal by 2, 5, or 10 according to the setting of the A/D trigger control register in the
corresponding channels.
19.3.2 PWM Operation
Channels 0 and 1 can be unconditionally used as PWM timers using external output pins (ADTO0A, ADTO0B, ADTO1A,
and ADTO1B).
When the prescaler is set using the A/D trigger control register (ADTCR) thus starting the free-running counter (ADCNT)
in channels 0 and 1, the counters increment the count value until the value matches the value in the corresponding cycle
register (ADCYLR). When the ADCNT value matches the ADCYLR value, the ADCNT value is cleared to H'0001, thus
incrementing again from H'0001. Here, the corresponding pins output 1 (0)*. When the appropriate value is set in the
duty register (ADDR) and the ADCNT matches the ADDR value, the corresponding pins output 0 (1)*. When the ADDR
value is H'0000, the output does not change (0% duty). To obtain the 100% duty output, set the same values to the ADDR
and ADCYLR. Note that the ADDR value should not be greater than the ADCYLR value.
Note: * Selected by the DTSEL0A, DTSEL0B, DTSEL1A, and DTSEL1B bits in the A/D trigger control register
(ADTCR).
Rev.3.00 Mar. 12, 2008 Page 528 of 948
REJ09B0177-0300