SH7059 Datasheet, PDF (64/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
25.2.1 Standby Control Register (SBYCR)
27.2.1 Standby Control Register (SBYCR)
945, 946
Description amended
The standby control register (SBYCR) is an 8-bit
readable/writable register that sets the transition to standby
mode, and the port state in standby mode. SBYCR is
initialized to H'1F by a power-on reset.
The standby control register (SBYCR) is an 8-bit
readable/writable register that sets the transition to standby
mode . SBYCR is initialized to H'1F by a power-on reset,
and set to H'3F in software standby mode.
Bit: 7
6
5
0
Bit: 7
6
5
0
SSBY HIZ
—
—
SSBY — SSBYF
—
Initial value: 0
0
0
1
Initial value: 0
0
0
1
R/W: R/W R/W
R
R
R/W: R/W
R
R
R
Bit 6: Port High Impedance (HIZ)
Bit 5: Reserved
25.2.2 System Control Register 1 (SYSCR1)
946, 947
Bit:
7
6
OSCSTOP INOSCE
Initial value: —
0
R/W:
R
R/W
0
RAME
1
R/W
Bits 6 and 5: Description amended
Bit 6: Reserved
Bit 5: Software Standby Flag (SSBYF)
27.2.2 System Control Register 1 (SYSCR1)
Bit table amended
Bit:
7
6
—
—
Initial value:
0
0
R/W:
R
R
0
RAME
1
R/W
• Bits 7 and 6: Refer to section 5.4, Precautions for
Performing Crystal Resonator Stoppage Detection
Function.
• Bits 7 to 2—Reserved: These bits are always read as 0.
The write value should always be 0.
• Bits 5 to 2—Reserved: These bits are always read as 0.
The write value should always be 0.
25.2.3 System Control Register 2 (SYSCR2)
27.2.3 System Control Register 2 (SYSCR2)
947
Bit 7: Description amended
Bit: 7
0
Bit: 7
0
CKSEL
MSTOP0
—
MSTOP0
Initial value: 0
1
Initial value: 0
1
R/W: R/W
R/W
R/W: R
R/W
• Bit 7—Internal Clock (φ) Select (CKSEL): See section
5, Clock Pulse Generator (CPG).
25.3.1 Transition to Hardware Standby Mode
949
Hardware standby mode reduces power consumption
drastically by halting all SH7058 functions. As the transition
to hardware standby mode is made by means of external
pin input, the transition is made asynchronously, regardless
of the current state of the SH7058, and therefore the chip
state prior to the transition is not preserved.
• Bit 7—Reserved: This bit is always read as 0 and
cannot be modified.
27.3.1 Transition to Hardware Standby Mode
Description amended
In hardware standby mode, power consumption is
drastically reduced by halting all the functions in this LSI
and stopping the internal power supply except the on-chip
RAM. Since the the transition to hardware standby mode is
made by external pin input, the transition is made
asynchronously, regardless of the current state of this LSI,
and internal power supply is stopped except the on-chip
RAM. Therefore the chip state prior to the transition is not
preserved.
Rev.3.00 Mar. 12, 2008 Page lxiv of xc
REJ09B0177-0300