SH7059 Datasheet, PDF (212/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
9.3.2 Wait State Control
The number of wait states inserted into external space access states can be controlled using the WCR settings (figure 9.4).
The specified number of T_W cycles are inserted as software cycles at the timing shown in figure 9.4.
T₁
T_W
T₂
CK
Address
Read
Data
Write
,
Data
Figure 9.4 Wait State Timing of External Space Access (Software Wait Only)
When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 9.5 shows
the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when the T_w state
shifts to the T₂ state. When using external waits, use a WCR setting of 1 state or more when extending CS assertion, and 2
states or more otherwise.
T₁
T_W
T_W
T_W0
T₂
CK
Address
Read
Write
Data
,
Data
Figure 9.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT Signal Wait State)
Rev.3.00 Mar. 12, 2008 Page 122 of 948
REJ09B0177-0300