SH7059 Datasheet, PDF (608/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
19.1.2 Block Diagram
Figure 19.1 shows a block diagram of the multi-trigger A/D converter.
A/D conversion part
Avcc
Avref
Avss
10-bit D/A
Timer control logic
Module data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
ATU0
ADTRG0
A/D timer part
Sample-and-
hold circuit
+
-
A/D conversion
control circuit
Priority
Timer control logic
Internal data bus
ADI0
ADT00A
ADT00B
ADT0
Avcc
Avref
Avss
A/D conversion part
10-bit D/A
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
ATU1
ADTRG1
A/D timer part
Module data bus
Module data bus
A/D conversion
+
control circuit
-
Priority
Timer control logic
Internal data bus
ADI1
ADT01A
ADT01B
ADT1
Module data bus
Figure 19.1 Simplified Block Diagram of Multi-Trigger A/D Converter
Rev.3.00 Mar. 12, 2008 Page 518 of 948
REJ09B0177-0300